diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2018-04-09 22:28:26 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-04-27 11:21:21 +0200 |
| commit | 5c8d08f3471265dfd2f6db6d381751848dbf7db3 (patch) | |
| tree | e61d63948fd2042401af352a11eee842a5a4f3c2 /include/dt-bindings/memory/tegra30-mc.h | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
dt-bindings: memory: tegra: Add hot resets definitions
Add definitions for the Tegra20+ memory controller hot resets.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings/memory/tegra30-mc.h')
| -rw-r--r-- | include/dt-bindings/memory/tegra30-mc.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 3cac81919023..169f005fbc78 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -22,4 +22,23 @@ #define TEGRA_SWGROUP_MPCORE 17 #define TEGRA_SWGROUP_ISP 18 +#define TEGRA30_MC_RESET_AFI 0 +#define TEGRA30_MC_RESET_AVPC 1 +#define TEGRA30_MC_RESET_DC 2 +#define TEGRA30_MC_RESET_DCB 3 +#define TEGRA30_MC_RESET_EPP 4 +#define TEGRA30_MC_RESET_2D 5 +#define TEGRA30_MC_RESET_HC 6 +#define TEGRA30_MC_RESET_HDA 7 +#define TEGRA30_MC_RESET_ISP 8 +#define TEGRA30_MC_RESET_MPCORE 9 +#define TEGRA30_MC_RESET_MPCORELP 10 +#define TEGRA30_MC_RESET_MPE 11 +#define TEGRA30_MC_RESET_3D 12 +#define TEGRA30_MC_RESET_3D2 13 +#define TEGRA30_MC_RESET_PPCS 14 +#define TEGRA30_MC_RESET_SATA 15 +#define TEGRA30_MC_RESET_VDE 16 +#define TEGRA30_MC_RESET_VI 17 + #endif |