Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
 "After a somewhat quiet 5.17 release, the size of the DT changes is a
  bit larger again. There are nine new SoC that get added, all of them
  related to existing platforms:

   - Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB

   - Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
     tablet

   - Microchip Lan966 networking SoC and it evaluation board

   - Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
     5X and Fairphone FP3 phones

   - Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
     with their evaluation boards

   - Samsung Exynos 850 phone SoC and reference board

   - Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone

   - Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
     from the Samsung Exynos family.

   - TI K3/AM62 SoC and reference board

  Support for additional functionality in existing dts files is added
  all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
  Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
  Broadcom.

  Samsung has a rework for its pinctrl schema that is a bit tricky and
  requires driver changes to be included here.

  A few more platforms only have smaller cleanups and DT Schema fixes,
  this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.

  The new machines are really too many to list, but I'll do it anyway:

  Allwinner:
   - A20-Marsboard development board

  Amlogic:
   - Amediatek X96-AIR (Amlogic S905X3)
   - CYX A95XF3-AIR (Amlogic S905X3)
   - Haochuangy H96-Max (Amlogic S905X3)
   - Amlogic AQ222 (Amlogic S4)
   - OSMC Vero 4K+ (Amlogic S905D)

  Arm Juno:
   - Separate DT depending on SCMI firmware version

  Aspeed:
   - Quanta S6Q BMC (AST2600)
   - ASRock ROMED8HM3 (AST2500)

  Broadcom:
   - Raspberry Pi Zero 2 W

  Marvell MVEBU/Armada:
   - Ctera C200 V1 NAS (kirkwood)
   - Ctera C200 V2 NAS (armada-370)

  Mstar:
   - DongShanPiOne, a low-end embedded board
   - Miyoo Mini handheld game console

  NXP i.MX:
   - Numerous i.MX8M Mini based boards in even more variations, but
    none based on other SoCs this time:
    Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
    Gateworks GW7903

  Qualcomm:
   - Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
   - SHIFT6mq phone (Snapdragon 845)
   - Samsung Galaxy Book2 (Snapdragon 850)
   - Snapdragon 8 Gen 1 Hardware Development Kit

  TI OMAP:
   - SanCloud BeagleBone Enhanced WiFi

  Rockchip:
   - Pine64 PineNote ereader tablet (rk356x)
   - Bananapi-R2-Pro (rk356x)

  STM32:
   - emtrion emSBS-Argon embedded board (stm32mp157c)"

* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
  arm64: dts: n5x: drop invalid property and fix edac node name
  arm64: dts: fsd: Add the MCT support
  arm64: dts: stingray: Fix spi clock name
  arm64: dts: ns2: Fix spi clock name
  ARM: dts: rockchip: Update regulator name for PX3
  ARM: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
  arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
  ARM: dts: at91: sama7g5: Add NAND support
  ARM: dts: at91: sama7g5: add eic node
  ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
  ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
  arm64: dts: lg: align pl330 node name with dtschema
  arm64: dts: lg: add dma-cells to pl330 node
  arm64: dts: juno: align pl330 node name with dtschema
  arm64: dts: broadcom: Fix sata nodename
  arm64: dts: n5x: add sdr edac support
  arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
  dt-bindings: usb: dwc2: add disable-over-current
  ...

9 files changed, 543 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index 98e1b2ab6403..8498c0cd95fe 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -35,6 +35,7 @@
 #define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
 #define PMC_ETHPLL		(PMC_MAIN + 8)
 #define PMC_CPU			(PMC_MAIN + 9)
+#define PMC_MCK1		(PMC_MAIN + 10)
 
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h
index 90c0f3dc1ba1..d9d7b8b4f426 100644
--- a/include/dt-bindings/clock/r9a06g032-sysctrl.h
+++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h
@@ -74,6 +74,7 @@
 #define R9A06G032_CLK_DDRPHY_PCLK	81	/* AKA CLK_REF_SYNC_D4 */
 #define R9A06G032_CLK_FW		81	/* AKA CLK_REF_SYNC_D4 */
 #define R9A06G032_CLK_CRYPTO		81	/* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_WATCHDOG		82	/* AKA CLK_REF_SYNC_D8 */
 #define R9A06G032_CLK_A7MP		84	/* AKA DIV_CA7 */
 #define R9A06G032_HCLK_CAN0		85
 #define R9A06G032_HCLK_CAN1		86
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
new file mode 100644
index 000000000000..43f4dbda872c
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G054 CPG Core Clocks */
+#define R9A07G054_CLK_I			0
+#define R9A07G054_CLK_I2		1
+#define R9A07G054_CLK_G			2
+#define R9A07G054_CLK_S0		3
+#define R9A07G054_CLK_S1		4
+#define R9A07G054_CLK_SPI0		5
+#define R9A07G054_CLK_SPI1		6
+#define R9A07G054_CLK_SD0		7
+#define R9A07G054_CLK_SD1		8
+#define R9A07G054_CLK_M0		9
+#define R9A07G054_CLK_M1		10
+#define R9A07G054_CLK_M2		11
+#define R9A07G054_CLK_M3		12
+#define R9A07G054_CLK_M4		13
+#define R9A07G054_CLK_HP		14
+#define R9A07G054_CLK_TSU		15
+#define R9A07G054_CLK_ZT		16
+#define R9A07G054_CLK_P0		17
+#define R9A07G054_CLK_P1		18
+#define R9A07G054_CLK_P2		19
+#define R9A07G054_CLK_AT		20
+#define R9A07G054_OSCCLK		21
+#define R9A07G054_CLK_P0_DIV2		22
+#define R9A07G054_CLK_DRP_M		23
+#define R9A07G054_CLK_DRP_D		24
+#define R9A07G054_CLK_DRP_A		25
+
+/* R9A07G054 Module Clocks */
+#define R9A07G054_CA55_SCLK		0
+#define R9A07G054_CA55_PCLK		1
+#define R9A07G054_CA55_ATCLK		2
+#define R9A07G054_CA55_GICCLK		3
+#define R9A07G054_CA55_PERICLK		4
+#define R9A07G054_CA55_ACLK		5
+#define R9A07G054_CA55_TSCLK		6
+#define R9A07G054_GIC600_GICCLK		7
+#define R9A07G054_IA55_CLK		8
+#define R9A07G054_IA55_PCLK		9
+#define R9A07G054_MHU_PCLK		10
+#define R9A07G054_SYC_CNT_CLK		11
+#define R9A07G054_DMAC_ACLK		12
+#define R9A07G054_DMAC_PCLK		13
+#define R9A07G054_OSTM0_PCLK		14
+#define R9A07G054_OSTM1_PCLK		15
+#define R9A07G054_OSTM2_PCLK		16
+#define R9A07G054_MTU_X_MCK_MTU3	17
+#define R9A07G054_POE3_CLKM_POE		18
+#define R9A07G054_GPT_PCLK		19
+#define R9A07G054_POEG_A_CLKP		20
+#define R9A07G054_POEG_B_CLKP		21
+#define R9A07G054_POEG_C_CLKP		22
+#define R9A07G054_POEG_D_CLKP		23
+#define R9A07G054_WDT0_PCLK		24
+#define R9A07G054_WDT0_CLK		25
+#define R9A07G054_WDT1_PCLK		26
+#define R9A07G054_WDT1_CLK		27
+#define R9A07G054_WDT2_PCLK		28
+#define R9A07G054_WDT2_CLK		29
+#define R9A07G054_SPI_CLK2		30
+#define R9A07G054_SPI_CLK		31
+#define R9A07G054_SDHI0_IMCLK		32
+#define R9A07G054_SDHI0_IMCLK2		33
+#define R9A07G054_SDHI0_CLK_HS		34
+#define R9A07G054_SDHI0_ACLK		35
+#define R9A07G054_SDHI1_IMCLK		36
+#define R9A07G054_SDHI1_IMCLK2		37
+#define R9A07G054_SDHI1_CLK_HS		38
+#define R9A07G054_SDHI1_ACLK		39
+#define R9A07G054_GPU_CLK		40
+#define R9A07G054_GPU_AXI_CLK		41
+#define R9A07G054_GPU_ACE_CLK		42
+#define R9A07G054_ISU_ACLK		43
+#define R9A07G054_ISU_PCLK		44
+#define R9A07G054_H264_CLK_A		45
+#define R9A07G054_H264_CLK_P		46
+#define R9A07G054_CRU_SYSCLK		47
+#define R9A07G054_CRU_VCLK		48
+#define R9A07G054_CRU_PCLK		49
+#define R9A07G054_CRU_ACLK		50
+#define R9A07G054_MIPI_DSI_PLLCLK	51
+#define R9A07G054_MIPI_DSI_SYSCLK	52
+#define R9A07G054_MIPI_DSI_ACLK		53
+#define R9A07G054_MIPI_DSI_PCLK		54
+#define R9A07G054_MIPI_DSI_VCLK		55
+#define R9A07G054_MIPI_DSI_LPCLK	56
+#define R9A07G054_LCDC_CLK_A		57
+#define R9A07G054_LCDC_CLK_P		58
+#define R9A07G054_LCDC_CLK_D		59
+#define R9A07G054_SSI0_PCLK2		60
+#define R9A07G054_SSI0_PCLK_SFR		61
+#define R9A07G054_SSI1_PCLK2		62
+#define R9A07G054_SSI1_PCLK_SFR		63
+#define R9A07G054_SSI2_PCLK2		64
+#define R9A07G054_SSI2_PCLK_SFR		65
+#define R9A07G054_SSI3_PCLK2		66
+#define R9A07G054_SSI3_PCLK_SFR		67
+#define R9A07G054_SRC_CLKP		68
+#define R9A07G054_USB_U2H0_HCLK		69
+#define R9A07G054_USB_U2H1_HCLK		70
+#define R9A07G054_USB_U2P_EXR_CPUCLK	71
+#define R9A07G054_USB_PCLK		72
+#define R9A07G054_ETH0_CLK_AXI		73
+#define R9A07G054_ETH0_CLK_CHI		74
+#define R9A07G054_ETH1_CLK_AXI		75
+#define R9A07G054_ETH1_CLK_CHI		76
+#define R9A07G054_I2C0_PCLK		77
+#define R9A07G054_I2C1_PCLK		78
+#define R9A07G054_I2C2_PCLK		79
+#define R9A07G054_I2C3_PCLK		80
+#define R9A07G054_SCIF0_CLK_PCK		81
+#define R9A07G054_SCIF1_CLK_PCK		82
+#define R9A07G054_SCIF2_CLK_PCK		83
+#define R9A07G054_SCIF3_CLK_PCK		84
+#define R9A07G054_SCIF4_CLK_PCK		85
+#define R9A07G054_SCI0_CLKP		86
+#define R9A07G054_SCI1_CLKP		87
+#define R9A07G054_IRDA_CLKP		88
+#define R9A07G054_RSPI0_CLKB		89
+#define R9A07G054_RSPI1_CLKB		90
+#define R9A07G054_RSPI2_CLKB		91
+#define R9A07G054_CANFD_PCLK		92
+#define R9A07G054_GPIO_HCLK		93
+#define R9A07G054_ADC_ADCLK		94
+#define R9A07G054_ADC_PCLK		95
+#define R9A07G054_TSU_PCLK		96
+#define R9A07G054_STPAI_INITCLK		97
+#define R9A07G054_STPAI_ACLK		98
+#define R9A07G054_STPAI_MCLK		99
+#define R9A07G054_STPAI_DCLKIN		100
+#define R9A07G054_STPAI_ACLK_DRP	101
+
+/* R9A07G054 Resets */
+#define R9A07G054_CA55_RST_1_0		0
+#define R9A07G054_CA55_RST_1_1		1
+#define R9A07G054_CA55_RST_3_0		2
+#define R9A07G054_CA55_RST_3_1		3
+#define R9A07G054_CA55_RST_4		4
+#define R9A07G054_CA55_RST_5		5
+#define R9A07G054_CA55_RST_6		6
+#define R9A07G054_CA55_RST_7		7
+#define R9A07G054_CA55_RST_8		8
+#define R9A07G054_CA55_RST_9		9
+#define R9A07G054_CA55_RST_10		10
+#define R9A07G054_CA55_RST_11		11
+#define R9A07G054_CA55_RST_12		12
+#define R9A07G054_GIC600_GICRESET_N	13
+#define R9A07G054_GIC600_DBG_GICRESET_N	14
+#define R9A07G054_IA55_RESETN		15
+#define R9A07G054_MHU_RESETN		16
+#define R9A07G054_DMAC_ARESETN		17
+#define R9A07G054_DMAC_RST_ASYNC	18
+#define R9A07G054_SYC_RESETN		19
+#define R9A07G054_OSTM0_PRESETZ		20
+#define R9A07G054_OSTM1_PRESETZ		21
+#define R9A07G054_OSTM2_PRESETZ		22
+#define R9A07G054_MTU_X_PRESET_MTU3	23
+#define R9A07G054_POE3_RST_M_REG	24
+#define R9A07G054_GPT_RST_C		25
+#define R9A07G054_POEG_A_RST		26
+#define R9A07G054_POEG_B_RST		27
+#define R9A07G054_POEG_C_RST		28
+#define R9A07G054_POEG_D_RST		29
+#define R9A07G054_WDT0_PRESETN		30
+#define R9A07G054_WDT1_PRESETN		31
+#define R9A07G054_WDT2_PRESETN		32
+#define R9A07G054_SPI_RST		33
+#define R9A07G054_SDHI0_IXRST		34
+#define R9A07G054_SDHI1_IXRST		35
+#define R9A07G054_GPU_RESETN		36
+#define R9A07G054_GPU_AXI_RESETN	37
+#define R9A07G054_GPU_ACE_RESETN	38
+#define R9A07G054_ISU_ARESETN		39
+#define R9A07G054_ISU_PRESETN		40
+#define R9A07G054_H264_X_RESET_VCP	41
+#define R9A07G054_H264_CP_PRESET_P	42
+#define R9A07G054_CRU_CMN_RSTB		43
+#define R9A07G054_CRU_PRESETN		44
+#define R9A07G054_CRU_ARESETN		45
+#define R9A07G054_MIPI_DSI_CMN_RSTB	46
+#define R9A07G054_MIPI_DSI_ARESET_N	47
+#define R9A07G054_MIPI_DSI_PRESET_N	48
+#define R9A07G054_LCDC_RESET_N		49
+#define R9A07G054_SSI0_RST_M2_REG	50
+#define R9A07G054_SSI1_RST_M2_REG	51
+#define R9A07G054_SSI2_RST_M2_REG	52
+#define R9A07G054_SSI3_RST_M2_REG	53
+#define R9A07G054_SRC_RST		54
+#define R9A07G054_USB_U2H0_HRESETN	55
+#define R9A07G054_USB_U2H1_HRESETN	56
+#define R9A07G054_USB_U2P_EXL_SYSRST	57
+#define R9A07G054_USB_PRESETN		58
+#define R9A07G054_ETH0_RST_HW_N		59
+#define R9A07G054_ETH1_RST_HW_N		60
+#define R9A07G054_I2C0_MRST		61
+#define R9A07G054_I2C1_MRST		62
+#define R9A07G054_I2C2_MRST		63
+#define R9A07G054_I2C3_MRST		64
+#define R9A07G054_SCIF0_RST_SYSTEM_N	65
+#define R9A07G054_SCIF1_RST_SYSTEM_N	66
+#define R9A07G054_SCIF2_RST_SYSTEM_N	67
+#define R9A07G054_SCIF3_RST_SYSTEM_N	68
+#define R9A07G054_SCIF4_RST_SYSTEM_N	69
+#define R9A07G054_SCI0_RST		70
+#define R9A07G054_SCI1_RST		71
+#define R9A07G054_IRDA_RST		72
+#define R9A07G054_RSPI0_RST		73
+#define R9A07G054_RSPI1_RST		74
+#define R9A07G054_RSPI2_RST		75
+#define R9A07G054_CANFD_RSTP_N		76
+#define R9A07G054_CANFD_RSTC_N		77
+#define R9A07G054_GPIO_RSTN		78
+#define R9A07G054_GPIO_PORT_RESETN	79
+#define R9A07G054_GPIO_SPARE_RESETN	80
+#define R9A07G054_ADC_PRESETN		81
+#define R9A07G054_ADC_ADRST_N		82
+#define R9A07G054_TSU_PRESETN		83
+#define R9A07G054_STPAI_ARESETN		84
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 8d7e66e1b6ef..8cae969e8cba 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
 
 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
@@ -9,6 +9,26 @@
  * @defgroup bpmp_clock_ids Clock ID's
  * @{
  */
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
+#define TEGRA234_CLK_AHUB			4U
+/** @brief output of gate CLK_ENB_APB2APE */
+#define TEGRA234_CLK_APB2APE			5U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
+#define TEGRA234_CLK_APE			6U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
+#define TEGRA234_CLK_AUD_MCLK			7U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
+#define TEGRA234_CLK_DMIC1			15U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
+#define TEGRA234_CLK_DMIC2			16U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
+#define TEGRA234_CLK_DMIC3			17U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
+#define TEGRA234_CLK_DMIC4			18U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
+#define TEGRA234_CLK_DSPK1			29U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
+#define TEGRA234_CLK_DSPK2			30U
 /**
  * @brief controls the EMC clock frequency.
  * @details Doing a clk_set_rate on this clock will select the
@@ -20,15 +40,126 @@
 #define TEGRA234_CLK_EMC			31U
 /** @brief output of gate CLK_ENB_FUSE */
 #define TEGRA234_CLK_FUSE			40U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
+#define TEGRA234_CLK_I2C1			48U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA234_CLK_I2C2			49U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA234_CLK_I2C3			50U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA234_CLK_I2C4			51U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA234_CLK_I2C6			52U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA234_CLK_I2C7			53U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA234_CLK_I2C8			54U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA234_CLK_I2C9			55U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
+#define TEGRA234_CLK_I2S1			56U
+/** @brief clock recovered from I2S1 input */
+#define TEGRA234_CLK_I2S1_SYNC_INPUT		57U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
+#define TEGRA234_CLK_I2S2			58U
+/** @brief clock recovered from I2S2 input */
+#define TEGRA234_CLK_I2S2_SYNC_INPUT		59U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
+#define TEGRA234_CLK_I2S3			60U
+/** @brief clock recovered from I2S3 input */
+#define TEGRA234_CLK_I2S3_SYNC_INPUT		61U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
+#define TEGRA234_CLK_I2S4			62U
+/** @brief clock recovered from I2S4 input */
+#define TEGRA234_CLK_I2S4_SYNC_INPUT		63U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
+#define TEGRA234_CLK_I2S5			64U
+/** @brief clock recovered from I2S5 input */
+#define TEGRA234_CLK_I2S5_SYNC_INPUT		65U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
+#define TEGRA234_CLK_I2S6			66U
+/** @brief clock recovered from I2S6 input */
+#define TEGRA234_CLK_I2S6_SYNC_INPUT		67U
+/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
+#define TEGRA234_CLK_PLLA			93U
+/** @brief PLLP clk output */
+#define TEGRA234_CLK_PLLP_OUT0			102U
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
+#define TEGRA234_CLK_PLLA_OUT0			104U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA234_CLK_PWM1			105U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA234_CLK_PWM2			106U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA234_CLK_PWM3			107U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA234_CLK_PWM4			108U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA234_CLK_PWM5			109U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA234_CLK_PWM6			110U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA234_CLK_PWM7			111U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA234_CLK_PWM8			112U
 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
 #define TEGRA234_CLK_SDMMC4			123U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
+#define TEGRA234_CLK_SYNC_DMIC1			139U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
+#define TEGRA234_CLK_SYNC_DMIC2			140U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
+#define TEGRA234_CLK_SYNC_DMIC3			141U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
+#define TEGRA234_CLK_SYNC_DMIC4			142U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
+#define TEGRA234_CLK_SYNC_DSPK1			143U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
+#define TEGRA234_CLK_SYNC_DSPK2			144U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
+#define TEGRA234_CLK_SYNC_I2S1			145U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
+#define TEGRA234_CLK_SYNC_I2S2			146U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
+#define TEGRA234_CLK_SYNC_I2S3			147U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
+#define TEGRA234_CLK_SYNC_I2S4			148U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
+#define TEGRA234_CLK_SYNC_I2S5			149U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
+#define TEGRA234_CLK_SYNC_I2S6			150U
 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
 #define TEGRA234_CLK_UARTA			155U
+/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
+#define TEGRA234_CLK_PEX1_C6_CORE		161U
+/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
+#define TEGRA234_CLK_PEX2_C7_CORE		171U
+/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
+#define TEGRA234_CLK_PEX2_C8_CORE		172U
+/** @brief output of gate CLK_ENB_PEX2_CORE_9 */
+#define TEGRA234_CLK_PEX2_C9_CORE		173U
+/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
+#define TEGRA234_CLK_PEX2_C10_CORE		187U
 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
 #define TEGRA234_CLK_SDMMC_LEGACY_TM		219U
+/** @brief output of gate CLK_ENB_PEX0_CORE_0 */
+#define TEGRA234_CLK_PEX0_C0_CORE		220U
+/** @brief output of gate CLK_ENB_PEX0_CORE_1 */
+#define TEGRA234_CLK_PEX0_C1_CORE		221U
+/** @brief output of gate CLK_ENB_PEX0_CORE_2 */
+#define TEGRA234_CLK_PEX0_C2_CORE		222U
+/** @brief output of gate CLK_ENB_PEX0_CORE_3 */
+#define TEGRA234_CLK_PEX0_C3_CORE		223U
+/** @brief output of gate CLK_ENB_PEX0_CORE_4 */
+#define TEGRA234_CLK_PEX0_C4_CORE		224U
+/** @brief output of gate CLK_ENB_PEX1_CORE_5 */
+#define TEGRA234_CLK_PEX1_C5_CORE		225U
 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
 #define TEGRA234_CLK_PLLC4			237U
 /** @brief 32K input clock provided by PMIC */
 #define TEGRA234_CLK_CLK_32K			289U
-
+/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
+#define TEGRA234_CLK_AZA_2XBIT			457U
+/** @brief aza_2xbitclk / 2 (aza_bitclk) */
+#define TEGRA234_CLK_AZA_BIT			458U
 #endif
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index 2662f70c15c6..e3b0e9da295d 100644
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
 
 #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
 #define DT_BINDINGS_MEMORY_TEGRA234_MC_H
@@ -7,15 +8,59 @@
 #define TEGRA234_SID_INVALID		0x00
 #define TEGRA234_SID_PASSTHROUGH	0x7f
 
+/* NISO0 stream IDs */
+#define TEGRA234_SID_APE	0x02
+#define TEGRA234_SID_HDA	0x03
+#define TEGRA234_SID_PCIE0	0x12
+#define TEGRA234_SID_PCIE4	0x13
+#define TEGRA234_SID_PCIE5	0x14
+#define TEGRA234_SID_PCIE6	0x15
+#define TEGRA234_SID_PCIE9	0x1f
 
 /* NISO1 stream IDs */
 #define TEGRA234_SID_SDMMC4	0x02
+#define TEGRA234_SID_PCIE1	0x05
+#define TEGRA234_SID_PCIE2	0x06
+#define TEGRA234_SID_PCIE3	0x07
+#define TEGRA234_SID_PCIE7	0x08
+#define TEGRA234_SID_PCIE8	0x09
+#define TEGRA234_SID_PCIE10	0x0b
 #define TEGRA234_SID_BPMP	0x10
 
 /*
  * memory client IDs
  */
 
+/* High-definition audio (HDA) read clients */
+#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
+/* PCIE6 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
+/* PCIE6 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
+/* PCIE7 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
+/* PCIE7 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
+/* PCIE8 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
+/* High-definition audio (HDA) write clients */
+#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
+/* PCIE8 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
+/* PCIE9 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
+/* PCIE6r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
+/* PCIE9 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
+/* PCIE10 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
+/* PCIE10 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
+/* PCIE10r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
+/* PCIE7r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
 /* sdmmcd memory read client */
 #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
 /* sdmmcd memory write client */
@@ -28,5 +73,35 @@
 #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
 /* BPMPDMA write client */
 #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
+/* APEDMA read client */
+#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
+/* APEDMA write client */
+#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
+/* PCIE0 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
+/* PCIE0 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
+/* PCIE1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
+/* PCIE1 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
+/* PCIE2 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
+/* PCIE2 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
+/* PCIE3 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
+/* PCIE3 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
+/* PCIE4 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
+/* PCIE4 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
+/* PCIE5 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
+/* PCIE5 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
+/* PCIE5r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
 
 #endif
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index 63e038e36ca3..a5204ab91d3e 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -41,4 +41,7 @@
 #define J721S2_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define J721S2_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define AM62X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM62X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
 #endif
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
new file mode 100644
index 000000000000..9f90c40a2c6c
--- /dev/null
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
+ */
+
+#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
+#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
+
+#define IMX8MP_POWER_DOMAIN_MIPI_PHY1			0
+#define IMX8MP_POWER_DOMAIN_PCIE_PHY			1
+#define IMX8MP_POWER_DOMAIN_USB1_PHY			2
+#define IMX8MP_POWER_DOMAIN_USB2_PHY			3
+#define IMX8MP_POWER_DOMAIN_MLMIX			4
+#define IMX8MP_POWER_DOMAIN_AUDIOMIX			5
+#define IMX8MP_POWER_DOMAIN_GPU2D			6
+#define IMX8MP_POWER_DOMAIN_GPUMIX			7
+#define IMX8MP_POWER_DOMAIN_VPUMIX			8
+#define IMX8MP_POWER_DOMAIN_GPU3D			9
+#define IMX8MP_POWER_DOMAIN_MEDIAMIX			10
+#define IMX8MP_POWER_DOMAIN_VPU_G1			11
+#define IMX8MP_POWER_DOMAIN_VPU_G2			12
+#define IMX8MP_POWER_DOMAIN_VPU_VC8000E			13
+#define IMX8MP_POWER_DOMAIN_HDMIMIX			14
+#define IMX8MP_POWER_DOMAIN_HDMI_PHY			15
+#define IMX8MP_POWER_DOMAIN_MIPI_PHY2			16
+#define IMX8MP_POWER_DOMAIN_HSIOMIX			17
+#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP		18
+
+#define IMX8MP_HSIOBLK_PD_USB				0
+#define IMX8MP_HSIOBLK_PD_USB_PHY1			1
+#define IMX8MP_HSIOBLK_PD_USB_PHY2			2
+#define IMX8MP_HSIOBLK_PD_PCIE				3
+#define IMX8MP_HSIOBLK_PD_PCIE_PHY			4
+
+#endif
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
new file mode 100644
index 000000000000..f610eee9bce8
--- /dev/null
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved. */
+
+#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
+#define __ABI_MACH_T234_POWERGATE_T234_H_
+
+#define TEGRA234_POWER_DOMAIN_AUD	2U
+#define TEGRA234_POWER_DOMAIN_DISP	3U
+#define TEGRA234_POWER_DOMAIN_PCIEX8A	5U
+#define TEGRA234_POWER_DOMAIN_PCIEX4A	6U
+#define TEGRA234_POWER_DOMAIN_PCIEX4BA	7U
+#define TEGRA234_POWER_DOMAIN_PCIEX4BB	8U
+#define TEGRA234_POWER_DOMAIN_PCIEX1A	9U
+#define TEGRA234_POWER_DOMAIN_PCIEX4CA	13U
+#define TEGRA234_POWER_DOMAIN_PCIEX4CB	14U
+#define TEGRA234_POWER_DOMAIN_PCIEX4CC	15U
+#define TEGRA234_POWER_DOMAIN_PCIEX8B	16U
+#define TEGRA234_POWER_DOMAIN_MGBEA	17U
+#define TEGRA234_POWER_DOMAIN_MGBEB	18U
+#define TEGRA234_POWER_DOMAIN_MGBEC	19U
+
+#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 50e13bced642..1362cd5e03f0 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
 
 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
 #define DT_BINDINGS_RESET_TEGRA234_RESET_H
@@ -10,8 +10,51 @@
  * @brief Identifiers for Resets controllable by firmware
  * @{
  */
+#define TEGRA234_RESET_PEX1_CORE_6		11U
+#define TEGRA234_RESET_PEX1_CORE_6_APB		12U
+#define TEGRA234_RESET_PEX1_COMMON_APB		13U
+#define TEGRA234_RESET_PEX2_CORE_7		14U
+#define TEGRA234_RESET_PEX2_CORE_7_APB		15U
+#define TEGRA234_RESET_HDA			20U
+#define TEGRA234_RESET_HDACODEC			21U
+#define TEGRA234_RESET_I2C1			24U
+#define TEGRA234_RESET_PEX2_CORE_8		25U
+#define TEGRA234_RESET_PEX2_CORE_8_APB		26U
+#define TEGRA234_RESET_PEX2_CORE_9		27U
+#define TEGRA234_RESET_PEX2_CORE_9_APB		28U
+#define TEGRA234_RESET_I2C2			29U
+#define TEGRA234_RESET_I2C3			30U
+#define TEGRA234_RESET_I2C4			31U
+#define TEGRA234_RESET_I2C6			32U
+#define TEGRA234_RESET_I2C7			33U
+#define TEGRA234_RESET_I2C8			34U
+#define TEGRA234_RESET_I2C9			35U
+#define TEGRA234_RESET_PEX2_CORE_10		56U
+#define TEGRA234_RESET_PEX2_CORE_10_APB		57U
+#define TEGRA234_RESET_PEX2_COMMON_APB		58U
+#define TEGRA234_RESET_PWM1			68U
+#define TEGRA234_RESET_PWM2			69U
+#define TEGRA234_RESET_PWM3			70U
+#define TEGRA234_RESET_PWM4			71U
+#define TEGRA234_RESET_PWM5			72U
+#define TEGRA234_RESET_PWM6			73U
+#define TEGRA234_RESET_PWM7			74U
+#define TEGRA234_RESET_PWM8			75U
 #define TEGRA234_RESET_SDMMC4			85U
 #define TEGRA234_RESET_UARTA			100U
+#define TEGRA234_RESET_PEX0_CORE_0		116U
+#define TEGRA234_RESET_PEX0_CORE_1		117U
+#define TEGRA234_RESET_PEX0_CORE_2		118U
+#define TEGRA234_RESET_PEX0_CORE_3		119U
+#define TEGRA234_RESET_PEX0_CORE_4		120U
+#define TEGRA234_RESET_PEX0_CORE_0_APB		121U
+#define TEGRA234_RESET_PEX0_CORE_1_APB		122U
+#define TEGRA234_RESET_PEX0_CORE_2_APB		123U
+#define TEGRA234_RESET_PEX0_CORE_3_APB		124U
+#define TEGRA234_RESET_PEX0_CORE_4_APB		125U
+#define TEGRA234_RESET_PEX0_COMMON_APB		126U
+#define TEGRA234_RESET_PEX1_CORE_5		129U
+#define TEGRA234_RESET_PEX1_CORE_5_APB		130U
 
 /** @} */