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authorRyder Lee <ryder.lee@mediatek.com>2018-03-06 17:09:26 +0800
committerStephen Boyd <sboyd@kernel.org>2018-03-19 13:40:57 -0700
commit936ceb12c5f72cd087149e3cf01347969a472801 (patch)
tree25255cf397c5ceef3f7ad9765e7d73efd263d61d /include/dt-bindings
parent89cd7aec21af26fd0c117bfc4bfc781724f201de (diff)
clk: mediatek: update missing clock data for MT7622 audsys
Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/mt7622-clk.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 3e514ed51d15..e9d77f0e8bce 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -235,7 +235,8 @@
#define CLK_AUDIO_MEM_ASRC3 43
#define CLK_AUDIO_MEM_ASRC4 44
#define CLK_AUDIO_MEM_ASRC5 45
-#define CLK_AUDIO_NR_CLK 46
+#define CLK_AUDIO_AFE_CONN 46
+#define CLK_AUDIO_NR_CLK 47
/* SSUSBSYS */