summaryrefslogtreecommitdiff
path: root/include/dt-bindings
diff options
context:
space:
mode:
authorStephen Boyd <sboyd@codeaurora.org>2017-06-02 10:51:41 -0700
committerStephen Boyd <sboyd@codeaurora.org>2017-06-02 10:51:41 -0700
commitf6b3130919eac29314f159563ebd3584821a294d (patch)
tree1b4543d45c88ad8b1cf3c8a4921b7adf3517a15b /include/dt-bindings
parent8fedfee49fb57244df8d96de1478eed79f45bd83 (diff)
parent14c735c8e3082714e3d5fa91843692a9c871cebe (diff)
Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clock driver updates from Jerome Brunet: * Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks * tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: Add EE 32K Clock for CEC clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 clk: meson: meson8b: mark clk81 as critical clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 3190e30b9398..e3e9f7919c31 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -5,7 +5,6 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
-#define CLKID_CPUCLK 1
#define CLKID_HDMI_PLL 2
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
@@ -13,24 +12,30 @@
#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
#define CLKID_MPLL2 15
+#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
#define CLKID_RNG0 25
+#define CLKID_UART0 26
#define CLKID_SPI 34
#define CLKID_ETH 36
#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40
#define CLKID_MIXER_IFACE 44
#define CLKID_AIU 47
+#define CLKID_UART1 48
#define CLKID_USB0 50
#define CLKID_USB1 51
#define CLKID_USB 55
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_UART2 68
#define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
@@ -42,5 +47,8 @@
#define CLKID_MALI_1_SEL 103
#define CLKID_MALI_1 105
#define CLKID_MALI 106
+#define CLKID_CTS_AMCLK 107
+#define CLKID_CTS_MCLK_I958 110
+#define CLKID_CTS_I958 113
#endif /* __GXBB_CLKC_H */