diff options
| author | Luca Weiss <luca.weiss@fairphone.com> | 2023-10-13 10:09:53 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-12-02 17:24:58 -0800 |
| commit | 18c74d56fe6070c7c38058d7b43ccf2102abebcd (patch) | |
| tree | 298ce30d256927acdd14b4302a4ed1926116c2d0 /include/dt-bindings | |
| parent | 725be1d6318e4ea7e3947fd4242a14cf589cfebf (diff) | |
iio: adc: Add PM7325 PMIC7 ADC bindings
Add the defines for the ADC channels found on the PM7325. The list is
taken from downstream msm-5.4 and adjusted for mainline.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20231013-fp5-thermals-v1-1-f14df01922e6@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h new file mode 100644 index 000000000000..96908014e09e --- /dev/null +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H +#define _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H + +#ifndef PM7325_SID +#define PM7325_SID 1 +#endif + +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +/* ADC channels for PM7325_ADC for PMIC7 */ +#define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND) +#define PM7325_ADC7_1P25VREF (PM7325_SID << 8 | ADC7_1P25VREF) +#define PM7325_ADC7_VREF_VADC (PM7325_SID << 8 | ADC7_VREF_VADC) +#define PM7325_ADC7_DIE_TEMP (PM7325_SID << 8 | ADC7_DIE_TEMP) + +#define PM7325_ADC7_AMUX_THM1 (PM7325_SID << 8 | ADC7_AMUX_THM1) +#define PM7325_ADC7_AMUX_THM2 (PM7325_SID << 8 | ADC7_AMUX_THM2) +#define PM7325_ADC7_AMUX_THM3 (PM7325_SID << 8 | ADC7_AMUX_THM3) +#define PM7325_ADC7_AMUX_THM4 (PM7325_SID << 8 | ADC7_AMUX_THM4) +#define PM7325_ADC7_AMUX_THM5 (PM7325_SID << 8 | ADC7_AMUX_THM5) +#define PM7325_ADC7_GPIO1 (PM7325_SID << 8 | ADC7_GPIO1) +#define PM7325_ADC7_GPIO2 (PM7325_SID << 8 | ADC7_GPIO2) +#define PM7325_ADC7_GPIO3 (PM7325_SID << 8 | ADC7_GPIO3) +#define PM7325_ADC7_GPIO4 (PM7325_SID << 8 | ADC7_GPIO4) + +/* 30k pull-up1 */ +#define PM7325_ADC7_AMUX_THM1_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_30K_PU) +#define PM7325_ADC7_AMUX_THM2_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_30K_PU) +#define PM7325_ADC7_AMUX_THM3_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_30K_PU) +#define PM7325_ADC7_AMUX_THM4_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_30K_PU) +#define PM7325_ADC7_AMUX_THM5_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_30K_PU) +#define PM7325_ADC7_GPIO1_30K_PU (PM7325_SID << 8 | ADC7_GPIO1_30K_PU) +#define PM7325_ADC7_GPIO2_30K_PU (PM7325_SID << 8 | ADC7_GPIO2_30K_PU) +#define PM7325_ADC7_GPIO3_30K_PU (PM7325_SID << 8 | ADC7_GPIO3_30K_PU) +#define PM7325_ADC7_GPIO4_30K_PU (PM7325_SID << 8 | ADC7_GPIO4_30K_PU) + +/* 100k pull-up2 */ +#define PM7325_ADC7_AMUX_THM1_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_100K_PU) +#define PM7325_ADC7_AMUX_THM2_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_100K_PU) +#define PM7325_ADC7_AMUX_THM3_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_100K_PU) +#define PM7325_ADC7_AMUX_THM4_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_100K_PU) +#define PM7325_ADC7_AMUX_THM5_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_100K_PU) +#define PM7325_ADC7_GPIO1_100K_PU (PM7325_SID << 8 | ADC7_GPIO1_100K_PU) +#define PM7325_ADC7_GPIO2_100K_PU (PM7325_SID << 8 | ADC7_GPIO2_100K_PU) +#define PM7325_ADC7_GPIO3_100K_PU (PM7325_SID << 8 | ADC7_GPIO3_100K_PU) +#define PM7325_ADC7_GPIO4_100K_PU (PM7325_SID << 8 | ADC7_GPIO4_100K_PU) + +/* 400k pull-up3 */ +#define PM7325_ADC7_AMUX_THM1_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_400K_PU) +#define PM7325_ADC7_AMUX_THM2_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_400K_PU) +#define PM7325_ADC7_AMUX_THM3_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_400K_PU) +#define PM7325_ADC7_AMUX_THM4_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_400K_PU) +#define PM7325_ADC7_AMUX_THM5_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_400K_PU) +#define PM7325_ADC7_GPIO1_400K_PU (PM7325_SID << 8 | ADC7_GPIO1_400K_PU) +#define PM7325_ADC7_GPIO2_400K_PU (PM7325_SID << 8 | ADC7_GPIO2_400K_PU) +#define PM7325_ADC7_GPIO3_400K_PU (PM7325_SID << 8 | ADC7_GPIO3_400K_PU) +#define PM7325_ADC7_GPIO4_400K_PU (PM7325_SID << 8 | ADC7_GPIO4_400K_PU) + +/* 1/3 Divider */ +#define PM7325_ADC7_GPIO4_DIV3 (PM7325_SID << 8 | ADC7_GPIO4_DIV3) + +#define PM7325_ADC7_VPH_PWR (PM7325_SID << 8 | ADC7_VPH_PWR) + +#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H */ |