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authorStephen Boyd <sboyd@codeaurora.org>2017-10-31 14:52:21 -0700
committerStephen Boyd <sboyd@codeaurora.org>2017-10-31 14:52:21 -0700
commitffc3eb6f3a836ad2c05040989ac3ae7a113efcdd (patch)
treeb917d0fc5d38dc845c197e46fb9ff6c60d66fb0f /include/dt-bindings
parentae74ac0828868af3295395be7bc892e0d0aba376 (diff)
parent4328a2186e5120cfd34c4f04c6e4b7e74fb8b7b4 (diff)
Merge tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock driver updates from Maxime Ripard: - Addition of sigma/delta modulation for the audio PLLs on the newer SoCs - A83t Display clocks supports - minor fixes that didn't have any impact on current features * tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun4i: Export video PLLs clk: sunxi-ng: Add A83T display clocks clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun4i: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL clk: sunxi-ng: nm: Add support for sigma-delta modulation clk: sunxi-ng: Add sigma-delta modulation support clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider clk: sunxi-ng: a83t: Fix invalid csi-mclk mux offset clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision clk: sunxi-ng: sun6i: Export video PLLs clk: sunxi-ng: Implement reset control status readback clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.c clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/sun4i-a10-ccu.h2
-rw-r--r--include/dt-bindings/clock/sun6i-a31-ccu.h4
2 files changed, 6 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
index c5a53f38d654..e4fa61be5c75 100644
--- a/include/dt-bindings/clock/sun4i-a10-ccu.h
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -43,6 +43,8 @@
#define _DT_BINDINGS_CLK_SUN4I_A10_H_
#define CLK_HOSC 1
+#define CLK_PLL_VIDEO0_2X 9
+#define CLK_PLL_VIDEO1_2X 18
#define CLK_CPU 20
/* AHB Gates */
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
index 4482530fb6f5..c5d13340184a 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -43,8 +43,12 @@
#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
#define _DT_BINDINGS_CLK_SUN6I_A31_H_
+#define CLK_PLL_VIDEO0_2X 7
+
#define CLK_PLL_PERIPH 10
+#define CLK_PLL_VIDEO1_2X 13
+
#define CLK_CPU 18
#define CLK_AHB1_MIPIDSI 23