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authorTero Kristo <t-kristo@ti.com>2016-03-16 21:54:55 +0200
committerStephen Boyd <sboyd@codeaurora.org>2016-04-15 17:26:18 -0700
commitc5cc2a0bc930f1ae00b198aeb752acc3bdd4d5a7 (patch)
tree3ea618128d355ba5553f2af10e8eb8ad6555b4d0 /include/linux/clk
parentfefe0535b74f7d577af9310cf3741b4960a6687f (diff)
clk: ti: dpll: add support for specifying max rate for DPLLs
DPLLs typically have a maximum rate they can support, and this varies from DPLL to DPLL. Add support of the maximum rate value to the DPLL data struct, and also add check for this in the DPLL round_rate function. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/linux/clk')
-rw-r--r--include/linux/clk/ti.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index dc5164a6df29..6110fe09ed18 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -37,6 +37,7 @@
* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
* @min_divider: minimum valid non-bypass divider value (actual)
* @max_divider: maximum valid non-bypass divider value (actual)
+ * @max_rate: maximum clock rate for the DPLL
* @modes: possible values of @enable_mask
* @autoidle_reg: register containing the DPLL autoidle mode bitfield
* @idlest_reg: register containing the DPLL idle status bitfield
@@ -81,6 +82,7 @@ struct dpll_data {
u8 last_rounded_n;
u8 min_divider;
u16 max_divider;
+ unsigned long max_rate;
u8 modes;
void __iomem *autoidle_reg;
void __iomem *idlest_reg;