summaryrefslogtreecommitdiff
path: root/include/linux/clk
diff options
context:
space:
mode:
authorPeter De Schrijver <pdeschrijver@nvidia.com>2018-01-25 16:00:12 +0200
committerThierry Reding <treding@nvidia.com>2018-03-08 19:18:08 +0100
commite403d00573431e1e3de1710a91c6090c60ec16af (patch)
tree5f6822fecb0e38b045b2fcf1a2848920cace7542 /include/linux/clk
parentcbfc8d0a85aa72ad66227c69b08904143dc73bbb (diff)
clk: tegra: MBIST work around for Tegra210
Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a domain. The reason is that the logic responsible for resetting the memory built-in self test mode can come up in an undefined state because its clock is gated by a second level clock gate (SLCG). Work around this by making sure the logic will get some clock edges by ensuring the relevant clock is enabled and temporarily override the relevant SLCGs. Unfortunately for some IP blocks, the control bits for overriding the SLCGs are not in CAR, but in the IP block itself. This means we need to map a few extra register banks in the clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Hector Martin <marcan@marcan.st> Tested-by: Andre Heider <a.heider@gmail.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> fixup mbist
Diffstat (limited to 'include/linux/clk')
-rw-r--r--include/linux/clk/tegra.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index d23c9cf26993..afb9edfa5d58 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -128,5 +128,6 @@ extern void tegra210_sata_pll_hw_sequence_start(void);
extern void tegra210_set_sata_pll_seq_sw(bool state);
extern void tegra210_put_utmipll_in_iddq(void);
extern void tegra210_put_utmipll_out_iddq(void);
+extern int tegra210_clk_handle_mbist_war(unsigned int id);
#endif /* __LINUX_CLK_TEGRA_H_ */