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authorJani Nikula <jani.nikula@intel.com>2017-09-28 15:56:49 +0300
committerJani Nikula <jani.nikula@intel.com>2017-09-28 15:56:49 +0300
commit32f35b863451884e856f0f577474740561a87fad (patch)
tree2d1d55c7e2d23e27197bf84246c5f23070eb0fce /include/linux/coresight-pmu.h
parentae7617f0ef1820be033eef93859a6bb6174a843f (diff)
parent754270c7c56292e97d0eff924a5d5d83f92add07 (diff)
Merge drm-upstream/drm-next into drm-intel-next-queued
Need MST sideband message transaction to power up/down nodes. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'include/linux/coresight-pmu.h')
-rw-r--r--include/linux/coresight-pmu.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h
index 7d410260661b..edfeaba95429 100644
--- a/include/linux/coresight-pmu.h
+++ b/include/linux/coresight-pmu.h
@@ -24,6 +24,12 @@
/* ETMv3.5/PTM's ETMCR config bit */
#define ETM_OPT_CYCACC 12
#define ETM_OPT_TS 28
+#define ETM_OPT_RETSTK 29
+
+/* ETMv4 CONFIGR programming bits for the ETM OPTs */
+#define ETM4_CFG_BIT_CYCACC 4
+#define ETM4_CFG_BIT_TS 11
+#define ETM4_CFG_BIT_RETSTK 12
static inline int coresight_get_trace_id(int cpu)
{