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authorMauro Carvalho Chehab <mchehab@redhat.com>2013-03-11 09:28:48 -0300
committerBorislav Petkov <bp@suse.de>2013-03-16 06:32:30 +0100
commit9713faecff3d071de1208b081d4943b002e9cb1c (patch)
treeb6ab68f15527eae952a407aa604607aca719a5ba /include/linux/edac.h
parent1eef1282549d7accdd33ee36d409b039b1f911fb (diff)
EDAC: Merge mci.mem_is_per_rank with mci.csbased
Both mci.mem_is_per_rank and mci.csbased denote the same thing: the memory controller is csrows based. Merge both fields into one. There's no need for the driver to actually fill it, as the core detects it by checking if one of the layers has the csrows type as part of the memory hierarchy: if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) per_rank = true; Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'include/linux/edac.h')
-rw-r--r--include/linux/edac.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/include/linux/edac.h b/include/linux/edac.h
index ab1ea98e767c..0b763276f619 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -675,11 +675,11 @@ struct mem_ctl_info {
* sees memory sticks ("dimms"), and the ones that sees memory ranks.
* All old memory controllers enumerate memories per rank, but most
* of the recent drivers enumerate memories per DIMM, instead.
- * When the memory controller is per rank, mem_is_per_rank is true.
+ * When the memory controller is per rank, csbased is true.
*/
unsigned n_layers;
struct edac_mc_layer *layers;
- bool mem_is_per_rank;
+ bool csbased;
/*
* DIMM info. Will eventually remove the entire csrows_info some day
@@ -740,8 +740,6 @@ struct mem_ctl_info {
u32 fake_inject_ue;
u16 fake_inject_count;
#endif
- __u8 csbased : 1, /* csrow-based memory controller */
- __resv : 7;
};
#endif