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authorDavid Woodhouse <David.Woodhouse@intel.com>2015-10-07 15:37:03 +0100
committerDavid Woodhouse <David.Woodhouse@intel.com>2015-10-15 13:22:41 +0100
commit1208225cf48fa3b170b6dfe7369f15c295260755 (patch)
tree0959dd52510c30e2dfe9e7608c25994ff5996bbf /include/linux/intel-iommu.h
parent907fea3491d52063bb37b1f1ce0cf8a4ae70944c (diff)
iommu/vt-d: Generalise DMAR MSI setup to allow for page request events
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/intel-iommu.h')
-rw-r--r--include/linux/intel-iommu.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 46add607567b..f16a2b9124d1 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -60,6 +60,14 @@
#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
+#define DMAR_PQH_REG 0xc0 /* Page request queue head register */
+#define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
+#define DMAR_PQA_REG 0xd0 /* Page request queue address register */
+#define DMAR_PRS_REG 0xdc /* Page request status register */
+#define DMAR_PECTL_REG 0xe0 /* Page request event control register */
+#define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
+#define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
+#define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
#define OFFSET_STRIDE (9)
@@ -373,7 +381,7 @@ struct intel_iommu {
int seq_id; /* sequence id of the iommu */
int agaw; /* agaw of this iommu */
int msagaw; /* max sagaw of this iommu */
- unsigned int irq;
+ unsigned int irq, pr_irq;
u16 segment; /* PCI segment# */
unsigned char name[13]; /* Device Name */