diff options
| author | Sohil Mehta <sohil.mehta@intel.com> | 2017-12-20 11:59:26 -0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2018-01-17 15:02:50 +0100 |
| commit | f1ac10c24efbbcba0f8dae37ee90d45847f5c5af (patch) | |
| tree | dfc517909ee0e7bd723dd37dace984008ba51dab /include/linux/intel-iommu.h | |
| parent | 59103caa6839592788e7ad58b35863aac034631a (diff) | |
iommu/vt-d: Add a check for 5-level paging support
Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/linux/intel-iommu.h')
| -rw-r--r-- | include/linux/intel-iommu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index a56bab114f39..8dad3dd26eae 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -83,6 +83,7 @@ /* * Decoding Capability Register */ +#define cap_5lp_support(c) (((c) >> 60) & 1) #define cap_pi_support(c) (((c) >> 59) & 1) #define cap_fl1gp_support(c) (((c) >> 56) & 1) #define cap_read_drain(c) (((c) >> 55) & 1) |