diff options
| author | Lu Baolu <baolu.lu@linux.intel.com> | 2021-03-20 10:54:13 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2021-04-07 11:55:47 +0200 |
| commit | c0474a606ecb9326227b4d68059942f9db88a897 (patch) | |
| tree | 4fda2b0c23bf96050e1faaac328b951a94327e64 /include/linux/intel-iommu.h | |
| parent | eea53c5816889ee8b64544fa2e9311a81184ff9c (diff) | |
iommu/vt-d: Invalidate PASID cache when root/context entry changed
When the Intel IOMMU is operating in the scalable mode, some information
from the root and context table may be used to tag entries in the PASID
cache. Software should invalidate the PASID-cache when changing root or
context table entries.
Suggested-by: Ashok Raj <ashok.raj@intel.com>
Fixes: 7373a8cc38197 ("iommu/vt-d: Setup context and enable RID2PASID support")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Link: https://lore.kernel.org/r/20210320025415.641201-4-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'include/linux/intel-iommu.h')
| -rw-r--r-- | include/linux/intel-iommu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index e0f8c2ade3e8..03faf20a6817 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -378,6 +378,7 @@ enum { /* PASID cache invalidation granu */ #define QI_PC_ALL_PASIDS 0 #define QI_PC_PASID_SEL 1 +#define QI_PC_GLOBAL 3 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) |