diff options
| author | Gabriel Somlo <gsomlo@gmail.com> | 2021-01-12 12:31:42 -0500 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2021-01-14 09:52:54 +0900 |
| commit | ffa4ebc48971abffed722b75887ac1d8c9256b41 (patch) | |
| tree | 7938734137b6d9133fb5681d4c5a0f4ce2281092 /include/linux/litex.h | |
| parent | b5d3061ea2e691ab1fa6465fce3c59d9d10357de (diff) | |
drivers/soc/litex: s/LITEX_REG_SIZE/LITEX_SUBREG_ALIGN/g
The constant LITEX_REG_SIZE is renamed to the more descriptive
LITEX_SUBREG_ALIGN (LiteX CSR subregisters are located at 32-bit
aligned MMIO addresses).
NOTE: this is a non-functional change.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'include/linux/litex.h')
| -rw-r--r-- | include/linux/litex.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/include/linux/litex.h b/include/linux/litex.h index 918bab45243c..c63a7e1a337c 100644 --- a/include/linux/litex.h +++ b/include/linux/litex.h @@ -20,10 +20,12 @@ * Supporting other configurations will require extending the logic in this * header and in the LiteX SoC controller driver. */ -#define LITEX_REG_SIZE 0x4 #define LITEX_SUBREG_SIZE 0x1 #define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8) +/* LiteX subregisters of any width are always aligned on a 4-byte boundary */ +#define LITEX_SUBREG_ALIGN 0x4 + static inline void _write_litex_subregister(u32 val, void __iomem *addr) { writel((u32 __force)cpu_to_le32(val), addr); @@ -36,11 +38,11 @@ static inline u32 _read_litex_subregister(void __iomem *addr) #define WRITE_LITEX_SUBREGISTER(val, base_offset, subreg_id) \ _write_litex_subregister(val, (base_offset) + \ - LITEX_REG_SIZE * (subreg_id)) + LITEX_SUBREG_ALIGN * (subreg_id)) #define READ_LITEX_SUBREGISTER(base_offset, subreg_id) \ _read_litex_subregister((base_offset) + \ - LITEX_REG_SIZE * (subreg_id)) + LITEX_SUBREG_ALIGN * (subreg_id)) /* * LiteX SoC Generator, depending on the configuration, can split a single |