diff options
| author | Hadar Hen Zion <hadarh@mellanox.com> | 2015-07-27 14:46:34 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2015-07-27 15:00:37 -0700 |
| commit | e38af4faf01d0b35df6995fb395e5fa4a4898289 (patch) | |
| tree | 67caf30865de860044d1dae8ee9c84b4cdc4d0eb /include/linux/mlx4/cq.h | |
| parent | e802f8e4c54e6adf4215ef9fa3d6eea8fcb10bf9 (diff) | |
net/mlx4_en: Add support for hardware accelerated 802.1ad vlan
To enable device support in accelerated 802.1ad vlan, the port
capability "packet has vlan enable" (phv_en) should be set.
Firmware won't work properly, in case phv_en is not set.
The user can enable "phv_en" port capability with the new ethtool
private flag phv-bit. The phv-bit private flag default value is OFF,
users who are interested in 802.1ad hardware acceleration should turn ON
the phv-bit private flag:
$ ethtool --set-priv-flags eth1 phv-bit on
Once the private flag is set, the device is ready for 802.1ad vlan
acceleration.
The user should also change the interface device features and turn on
"tx-vlan-stag-hw-insert" which is off by default:
$ ethtool -K eth1 tx-vlan-stag-hw-insert on
"phv-bit" private flag setting is available only for Physical
Functions(PF), the Virtual Function (VF) will be able to use the feature
by setting "tx-vlan-stag-hw-insert" ethtool device feature only if the
feature was enabled by the Hypervisor.
Signed-off-by: Hadar Hen Zion <hadarh@mellanox.com>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/mlx4/cq.h')
| -rw-r--r-- | include/linux/mlx4/cq.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h index 899a97b20d27..09cebe528488 100644 --- a/include/linux/mlx4/cq.h +++ b/include/linux/mlx4/cq.h @@ -89,6 +89,7 @@ struct mlx4_ts_cqe { enum { MLX4_CQE_L2_TUNNEL_IPOK = 1 << 31, MLX4_CQE_CVLAN_PRESENT_MASK = 1 << 29, + MLX4_CQE_SVLAN_PRESENT_MASK = 1 << 30, MLX4_CQE_L2_TUNNEL = 1 << 27, MLX4_CQE_L2_TUNNEL_CSUM = 1 << 26, MLX4_CQE_L2_TUNNEL_IPV4 = 1 << 25, |