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authorShay Drory <shayd@nvidia.com>2021-08-19 16:18:57 +0300
committerSaeed Mahameed <saeedm@nvidia.com>2021-10-04 18:10:57 -0700
commit3663ad34bc707fc85492f4d83a313f5df84718d4 (patch)
tree340ca277308e70b24c0c03417c4f9e05ec83fcbf /include/linux/mlx5
parent575baa92fd463cb202447fe14770532cae55715a (diff)
net/mlx5: Shift control IRQ to the last index
Control IRQ is the first IRQ vector. This complicates handling of completion irqs as we need to offset them by one. in the next patch, there are scenarios where completion and control EQs will share the same irq. for example: functions with single IRQ. To ease such scenarios, we shift control IRQ to the end of the irq array. Signed-off-by: Shay Drory <shayd@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/driver.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index e23417424373..0ca719c00824 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -59,6 +59,8 @@
#define MLX5_ADEV_NAME "mlx5_core"
+#define MLX5_IRQ_EQ_CTRL (U8_MAX)
+
enum {
MLX5_BOARD_ID_LEN = 64,
};