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authorTal Gilboa <talgi@nvidia.com>2021-02-11 10:55:49 +0200
committerJason Gunthorpe <jgg@nvidia.com>2021-02-16 14:42:59 -0400
commit7232c132d13aafd178ba18c1099b2cb98d104b8c (patch)
treeb6bffa876586ab59b02b4881eeff0bcb4ca37fb6 /include/linux/mlx5
parente2853c49477d104c01d3c7944e1fb5074eb11d9f (diff)
RDMA/mlx5: Allow CQ creation without attached EQs
The traditional DevX CQ creation flow goes through mlx5_core_create_cq() which checks that the given EQN corresponds to an existing EQ and attaches a devx handler to the EQN for the CQ. In some cases the EQ will not be a kernel EQ, but will be controlled by modify CQ, don't block creating these just because the EQN can't be found in the kernel. Link: https://lore.kernel.org/r/20210211085549.1277674-1-leon@kernel.org Signed-off-by: Tal Gilboa <talgi@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index cf692fc17f41..768e097c633b 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1634,7 +1634,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 sf_set_partition[0x1];
u8 reserved_at_682[0x1];
u8 log_max_sf[0x5];
- u8 reserved_at_688[0x8];
+ u8 apu[0x1];
+ u8 reserved_at_689[0x7];
u8 log_min_sf_size[0x8];
u8 max_num_sf_partitions[0x8];
@@ -3816,7 +3817,7 @@ struct mlx5_ifc_cqc_bits {
u8 status[0x4];
u8 reserved_at_4[0x2];
u8 dbr_umem_valid[0x1];
- u8 reserved_at_7[0x1];
+ u8 apu_thread_cq[0x1];
u8 cqe_sz[0x3];
u8 cc[0x1];
u8 reserved_at_c[0x1];