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authorMiquel Raynal <miquel.raynal@bootlin.com>2020-05-29 13:13:21 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2020-06-26 08:35:08 +0200
commita69ad11168dca68b3f0adc6882422f4a2e2cb050 (patch)
tree355a95802fcb032fbe9642e3c4d1d690e5808a39 /include/linux/mtd
parent6d469f863772946e9ebd26068f7c9a609ab128d3 (diff)
mtd: rawnand: Get rid of the default ONFI timing mode
The ->choose_interface() hook is here for manufacturer drivers to provide a better timing interface than the default one, this field is not needed anymore. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200529111322.7184-28-miquel.raynal@bootlin.com
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/rawnand.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 316a02189da1..a2427c67d38b 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1069,9 +1069,6 @@ struct nand_manufacturer {
* @options: Various chip options. They can partly be set to inform nand_scan
* about special functionality. See the defines for further
* explanation.
- * @onfi_timing_mode_default: Default ONFI timing mode. This field is set to the
- * actually used ONFI mode if the chip is ONFI
- * compliant or deduced from the datasheet otherwise
* @interface_config: NAND interface timing information
* @bbt_erase_shift: Number of address bits in a bbt entry
* @bbt_options: Bad block table specific options. All options used here must
@@ -1119,7 +1116,6 @@ struct nand_chip {
unsigned int options;
/* Data interface */
- int onfi_timing_mode_default;
struct nand_interface_config interface_config;
/* Bad block information */
@@ -1268,10 +1264,6 @@ nand_get_interface_config(struct nand_chip *chip)
* @ecc_step_ds in nand_chip{}, also from the datasheet.
* For example, the "4bit ECC for each 512Byte" can be set with
* NAND_ECC_INFO(4, 512).
- * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
- * reset. Should be deduced from timings described
- * in the datasheet.
- *
*/
struct nand_flash_dev {
char *name;
@@ -1292,7 +1284,6 @@ struct nand_flash_dev {
uint16_t strength_ds;
uint16_t step_ds;
} ecc;
- int onfi_timing_mode_default;
};
int nand_create_bbt(struct nand_chip *chip);