diff options
| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-01-07 13:07:38 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2019-01-07 17:57:13 +0530 |
| commit | 69da8be90d5e85e60b5377c47384154b9dabf592 (patch) | |
| tree | b83e230892a29f80ff1619823a5f1275375b199c /include/linux/platform_data/dma-dw.h | |
| parent | 078165779608873e7b6eae1316a39c73af9f3edc (diff) | |
dmaengine: dw: Split DW and iDMA 32-bit operations
Here is a kinda big refactoring that should have been done
in the first place, when Intel iDMA 32-bit support appeared.
It splits operations which are different to Synopsys DesignWare and
Intel iDMA 32-bit controllers.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux/platform_data/dma-dw.h')
| -rw-r--r-- | include/linux/platform_data/dma-dw.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index 1c85eeee4171..576048433809 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -38,7 +38,6 @@ struct dw_dma_slave { /** * struct dw_dma_platform_data - Controller configuration parameters * @nr_channels: Number of channels supported by hardware (max 8) - * @is_idma32: The type of the DMA controller is iDMA32 * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller @@ -50,7 +49,6 @@ struct dw_dma_slave { */ struct dw_dma_platform_data { unsigned int nr_channels; - bool is_idma32; #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ unsigned char chan_allocation_order; |