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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2021-07-12 14:39:40 +0300
committerVinod Koul <vkoul@kernel.org>2021-07-14 10:16:30 +0530
commitfe364a7d95c24e07e9b3f2ab917f01d6d8330bba (patch)
tree6a61242a541989d8c3cd78ef156cf6010610b632 /include/linux/platform_data/dma-dw.h
parente73f0f0ee7541171d89f2e2491130c7771ba58d3 (diff)
dmaengine: dw: Program xBAR hardware for Elkhart Lake
Intel Elkhart Lake PSE DMA implementation is integrated with crossbar IP in order to serve more hardware than there are DMA request lines available. Due to this, program xBAR hardware to make flexible support of PSE peripheral. The Device-to-Device has not been tested and it's not supported by DMA Engine, but it's left in the code for the sake of documenting hardware features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210712113940.42753-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux/platform_data/dma-dw.h')
-rw-r--r--include/linux/platform_data/dma-dw.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index b34a094b2258..b11b0c8bc5da 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -52,6 +52,7 @@ struct dw_dma_slave {
* @max_burst: Maximum value of burst transaction size supported by hardware
* per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
* @protctl: Protection control signals setting per channel.
+ * @quirks: Optional platform quirks.
*/
struct dw_dma_platform_data {
unsigned int nr_channels;
@@ -71,6 +72,8 @@ struct dw_dma_platform_data {
#define CHAN_PROTCTL_CACHEABLE BIT(2)
#define CHAN_PROTCTL_MASK GENMASK(2, 0)
unsigned char protctl;
+#define DW_DMA_QUIRK_XBAR_PRESENT BIT(0)
+ unsigned int quirks;
};
#endif /* _PLATFORM_DATA_DMA_DW_H */