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authorJarkko Nikula <jarkko.nikula@linux.intel.com>2015-06-04 16:55:11 +0300
committerMark Brown <broonie@kernel.org>2015-06-05 11:40:45 +0100
commitdccf7369652f3934456345aab6a92fa905177886 (patch)
tree2d942ae9e9a14483a0962c7a9858d0cf026e9e61 /include/linux/pxa2xx_ssp.h
parent03fbf488cece461468d3abb795f5e5f055e00040 (diff)
spi: pxa2xx: Prepare for new Intel LPSS SPI type
Some of the Intel LPSS SPI properties will be different in upcoming platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI private registers will be at different offset and there will be changes in individual registers and default FIFO thresholds too. Add configuration for these differences and use them in runtime based on LPSS SSP type. With this change private registers offset autodetection becomes needless. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/pxa2xx_ssp.h')
-rw-r--r--include/linux/pxa2xx_ssp.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 95a4b3bd7a5c..0485bab061fd 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -195,7 +195,7 @@ enum pxa_ssp_type {
PXA910_SSP,
CE4100_SSP,
QUARK_X1000_SSP,
- LPSS_LPT_SSP,
+ LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */
LPSS_BYT_SSP,
};