diff options
| author | Mika Westerberg <mika.westerberg@linux.intel.com> | 2016-02-08 17:14:31 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-02-09 19:01:11 +0000 |
| commit | 30f3a6ab44d8d06bb3d94f6320e4aa76df59d025 (patch) | |
| tree | 123be907145582b282d6054f163c14ec4ddc65aa /include/linux/pxa2xx_ssp.h | |
| parent | c1e4a53c6b8161ded3a44e3352ef38206d0967ea (diff) | |
spi: pxa2xx: Add support for both chip selects on Intel Braswell
Intel Braswell LPSS SPI controller actually has two chip selects and there
is no capabilities register where this could be found out. These two chip
selects are controlled by bits which are in slightly differrent location
than Broxton has.
Braswell Windows driver also starts chip select (ACPI DeviceSelection)
numbering from 1 so translate it to be suitable for Linux as well.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/pxa2xx_ssp.h')
| -rw-r--r-- | include/linux/pxa2xx_ssp.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index c2f2574ff61c..2a097d176ba9 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -197,6 +197,7 @@ enum pxa_ssp_type { QUARK_X1000_SSP, LPSS_LPT_SSP, /* Keep LPSS types sorted with lpss_platforms[] */ LPSS_BYT_SSP, + LPSS_BSW_SSP, LPSS_SPT_SSP, LPSS_BXT_SSP, }; |