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authorRicky Wu <ricky_wu@realtek.com>2020-07-06 15:02:59 +0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-07-10 14:58:47 +0200
commit849a9366cba92cb5dc9dc1161ef49416a290aae9 (patch)
tree614b3f74d69e5b32d4c4ef09cf3d57cd297245fe /include/linux/rtsx_pci.h
parentf31a03b123b1f849bc0f60493edb95342f2c8e9a (diff)
misc: rtsx: Add support new chip rts5228 mmc: rtsx: Add support MMC_CAP2_NO_MMC
In order to support new chip rts5228, the definitions of some internal registers and workflow have to be modified. Added rts5228.c rts5228.h for independent functions of the new chip rts5228 Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Link: https://lore.kernel.org/r/20200706070259.32565-1-ricky_wu@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/linux/rtsx_pci.h')
-rw-r--r--include/linux/rtsx_pci.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/linux/rtsx_pci.h b/include/linux/rtsx_pci.h
index e8780d4e4636..27a6ea82aeea 100644
--- a/include/linux/rtsx_pci.h
+++ b/include/linux/rtsx_pci.h
@@ -305,6 +305,8 @@
#define SD30_CLK_STOP_CFG0 0x01
#define REG_PRE_RW_MODE 0xFD70
#define EN_INFINITE_MODE 0x01
+#define REG_CRC_DUMMY_0 0xFD71
+#define CFG_SD_POW_AUTO_PD (1<<0)
#define SRCTL 0xFC13
@@ -599,6 +601,7 @@
#define ASPM_FORCE_CTL 0xFE57
#define FORCE_ASPM_CTL0 0x10
+#define FORCE_ASPM_CTL1 0x20
#define FORCE_ASPM_VAL_MASK 0x03
#define FORCE_ASPM_L1_EN 0x02
#define FORCE_ASPM_L0_EN 0x01
@@ -667,6 +670,11 @@
#define PM_WAKE_EN 0x01
#define PM_CTRL4 0xFF47
+#define REG_CFG_OOBS_OFF_TIMER 0xFEA6
+#define REG_CFG_OOBS_ON_TIMER 0xFEA7
+#define REG_CFG_VCM_ON_TIMER 0xFEA8
+#define REG_CFG_OOBS_POLLING 0xFEA9
+
/* Memory mapping */
#define SRAM_BASE 0xE600
#define RBUF_BASE 0xF400
@@ -1204,6 +1212,7 @@ struct rtsx_pcr {
#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
#define EXTRA_CAPS_MMC_HS200 (1 << 4)
#define EXTRA_CAPS_MMC_8BIT (1 << 5)
+#define EXTRA_CAPS_NO_MMC (1 << 7)
u32 extra_caps;
#define IC_VER_A 0
@@ -1242,6 +1251,7 @@ struct rtsx_pcr {
u8 dma_error_count;
u8 ocp_stat;
u8 ocp_stat2;
+ u8 rtd3_en;
};
#define PID_524A 0x524A
@@ -1250,6 +1260,7 @@ struct rtsx_pcr {
#define PID_525A 0x525A
#define PID_5260 0x5260
#define PID_5261 0x5261
+#define PID_5228 0x5228
#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
#define PCI_VID(pcr) ((pcr)->pci->vendor)