summaryrefslogtreecommitdiff
path: root/include/linux/sh_dma.h
diff options
context:
space:
mode:
authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2012-01-04 15:34:17 +0100
committerVinod Koul <vinod.koul@linux.intel.com>2012-01-06 11:40:11 +0530
commitc11b46c32c8a9bf05fdb76d70d8dc74fcbfd02d1 (patch)
tree970a85e6a577d878c5ee57f31a1ee3df0fb8ad00 /include/linux/sh_dma.h
parentf69f2e264f6388df6d3cae45dd67ddfd52aaa14b (diff)
dma: shdma: fix runtime PM: clear channel buffers on reset
On platforms, supporting power domains, if the domain, containing a DMAC instance is powered down, the driver fails to resume correctly. On those platforms DMAC channels have an additional CHCLR register for clearing channel buffers. Using this register during runtime resume fixes the problem. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Diffstat (limited to 'include/linux/sh_dma.h')
-rw-r--r--include/linux/sh_dma.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index 62ef6938da10..8cd7fe59cf1a 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -48,6 +48,7 @@ struct sh_dmae_channel {
unsigned int offset;
unsigned int dmars;
unsigned int dmars_bit;
+ unsigned int chclr_offset;
};
struct sh_dmae_pdata {
@@ -68,6 +69,7 @@ struct sh_dmae_pdata {
unsigned int dmaor_is_32bit:1;
unsigned int needs_tend_set:1;
unsigned int no_dmars:1;
+ unsigned int chclr_present:1;
};
/* DMA register */