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authorVoon Weifeng <weifeng.voon@intel.com>2019-08-27 09:38:11 +0800
committerDavid S. Miller <davem@davemloft.net>2019-08-27 21:59:38 -0700
commit190f73ab4c43ecfc8e93843fe249efeff7d69a90 (patch)
tree2fb35df8641af5aad5fdd0a4b276cb05932b136a /include/linux/stmmac.h
parentf6256585fecc9b9d2f0a335a92e864ccae98ea24 (diff)
net: stmmac: setup higher frequency clk support for EHL & TGL
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, ptp clock and ptp_max_adj to 200MHz. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/stmmac.h')
-rw-r--r--include/linux/stmmac.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 5cc6b6faf359..7ad7ae35cf88 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -168,6 +168,7 @@ struct plat_stmmacenet_data {
struct clk *clk_ptp_ref;
unsigned int clk_ptp_rate;
unsigned int clk_ref_rate;
+ s32 ptp_max_adj;
struct reset_control *stmmac_rst;
struct stmmac_axi *axi;
int has_gmac4;