diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-03-21 16:12:11 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-03-22 12:15:15 -0700 |
| commit | 2d72d5016f00fc7d64b95e79405787dea73669af (patch) | |
| tree | 93c606430c44ce66116de8d23e00a979ed19044a /include/linux/stmmac.h | |
| parent | 33e85b8dd69e7f2fbf77f04bfc97ea7c76bccf9b (diff) | |
net: stmmac: Use AVB mode by default
Prior to the recent multi-queue changes the driver would configure the
queues to use the AVB mode, but the mode then got switched to DCB. The
hardware still works fine in DCB mode, but my testing capabilities are
limited, so it's safer to revert to the prior setting anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-By: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/stmmac.h')
| -rw-r--r-- | include/linux/stmmac.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index cd98ee232ad1..3921cb9dfadb 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -56,8 +56,8 @@ #define MTL_RX_ALGORITHM_WSP 0x5 /* RX/TX Queue Mode */ -#define MTL_QUEUE_DCB 0x0 -#define MTL_QUEUE_AVB 0x1 +#define MTL_QUEUE_AVB 0x0 +#define MTL_QUEUE_DCB 0x1 /* The MDC clock could be set higher than the IEEE 802.3 * specified frequency limit 0f 2.5 MHz, by programming a clock divider |