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authorBoris Brezillon <bbrezillon@kernel.org>2018-11-04 16:09:42 +0100
committerMiquel Raynal <miquel.raynal@bootlin.com>2019-04-08 10:21:16 +0200
commit6a1b66d6c8d691b1395d5c3b660ac4469c25bc28 (patch)
treea912c891f509bdbe47c80c7f7e31d84885ca613a /include/linux
parent32813e288414fecce18f37f8f0d0414a64b45c56 (diff)
mtd: rawnand: Get rid of chip->ecc_{strength,step}_ds
nand_device embeds a nand_ecc_req object which contains the minimum strength and step-size required by the NAND device. Drop the chip->ecc_{strength,step}_ds fields and use chip->base.eccreq.{strength,step_size} instead. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mtd/rawnand.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 27c968d370bf..c0589f82c1f8 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -992,12 +992,6 @@ struct nand_legacy {
* @badblockbits: [INTERN] minimum number of set bits in a good block's
* bad block marker position; i.e., BBM == 11110111b is
* not bad when badblockbits == 7
- * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
- * Minimum amount of bit errors per @ecc_step_ds guaranteed
- * to be correctable. If unknown, set to zero.
- * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
- * also from the datasheet. It is the recommended ECC step
- * size, if known; if unknown, set to zero.
* @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
* set to the actually used ONFI mode if the chip is
* ONFI compliant or deduced from the datasheet if
@@ -1060,8 +1054,6 @@ struct nand_chip {
} pagecache;
int subpagesize;
- uint16_t ecc_strength_ds;
- uint16_t ecc_step_ds;
int onfi_timing_mode_default;
int badblockpos;
int badblockbits;