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authorPhilippe Bergheaud <felix@linux.ibm.com>2020-06-19 16:04:39 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2020-07-15 11:07:19 +1000
commit87db7579ebd5ded337056eb765542eb2608f16e3 (patch)
treec57c5124e686993625127553f9f92f3b4a56f4bc /include/misc
parentacccc984c1f2e49225b40f1d0d20d383ec27d4d0 (diff)
ocxl: control via sysfs whether the FPGA is reloaded on a link reset
Some opencapi FPGA images allow to control if the FPGA should be reloaded on the next adapter reset. If it is supported, the image specifies it through a Vendor Specific DVSEC in the config space of function 0. Signed-off-by: Philippe Bergheaud <felix@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200619140439.153962-1-fbarrat@linux.ibm.com
Diffstat (limited to 'include/misc')
-rw-r--r--include/misc/ocxl-config.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/misc/ocxl-config.h b/include/misc/ocxl-config.h
index 3526fa996a22..ccfd3b463517 100644
--- a/include/misc/ocxl-config.h
+++ b/include/misc/ocxl-config.h
@@ -41,5 +41,6 @@
#define OCXL_DVSEC_VENDOR_CFG_VERS 0x0C
#define OCXL_DVSEC_VENDOR_TLX_VERS 0x10
#define OCXL_DVSEC_VENDOR_DLX_VERS 0x20
+#define OCXL_DVSEC_VENDOR_RESET_RELOAD 0x38
#endif /* _OCXL_CONFIG_H_ */