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authorJiucheng Xu <jiucheng.xu@amlogic.com>2022-11-21 10:15:58 +0800
committerWill Deacon <will@kernel.org>2022-11-21 18:28:45 +0000
commit2016e2113d35ba06866961a39e9a9c822f2ffabd (patch)
treefea96e63ecba26725021998bb00492e4d9a7c9f5 /include/soc
parentdcc7f001b44c30a377f44413471217cecddbee9a (diff)
perf/amlogic: Add support for Amlogic meson G12 SoC DDR PMU driver
Add support for Amlogic Meson G12 Series SOC - DDR bandwidth PMU driver framework and interfaces. The PMU can not only monitor the total DDR bandwidth, but also individual IP module bandwidth. Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com> Tested-by: Chris Healy <healych@amazon.com> Link: https://lore.kernel.org/r/20221121021602.3306998-1-jiucheng.xu@amlogic.com Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/amlogic/meson_ddr_pmu.h66
1 files changed, 66 insertions, 0 deletions
diff --git a/include/soc/amlogic/meson_ddr_pmu.h b/include/soc/amlogic/meson_ddr_pmu.h
new file mode 100644
index 000000000000..4a33e4ab8ada
--- /dev/null
+++ b/include/soc/amlogic/meson_ddr_pmu.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_DDR_PMU_H__
+#define __MESON_DDR_PMU_H__
+
+#define MAX_CHANNEL_NUM 8
+
+enum {
+ ALL_CHAN_COUNTER_ID,
+ CHAN1_COUNTER_ID,
+ CHAN2_COUNTER_ID,
+ CHAN3_COUNTER_ID,
+ CHAN4_COUNTER_ID,
+ CHAN5_COUNTER_ID,
+ CHAN6_COUNTER_ID,
+ CHAN7_COUNTER_ID,
+ CHAN8_COUNTER_ID,
+ COUNTER_MAX_ID,
+};
+
+struct dmc_info;
+
+struct dmc_counter {
+ u64 all_cnt; /* The count of all requests come in/out ddr controller */
+ union {
+ u64 all_req;
+ struct {
+ u64 all_idle_cnt;
+ u64 all_16bit_cnt;
+ };
+ };
+ u64 channel_cnt[MAX_CHANNEL_NUM]; /* To save a DMC bandwidth-monitor channel counter */
+};
+
+struct dmc_hw_info {
+ void (*enable)(struct dmc_info *info);
+ void (*disable)(struct dmc_info *info);
+ /* Bind an axi line to a bandwidth-monitor channel */
+ void (*set_axi_filter)(struct dmc_info *info, int axi_id, int chann);
+ int (*irq_handler)(struct dmc_info *info,
+ struct dmc_counter *counter);
+ void (*get_counters)(struct dmc_info *info,
+ struct dmc_counter *counter);
+
+ int dmc_nr; /* The number of dmc controller */
+ int chann_nr; /* The number of dmc bandwidth monitor channels */
+ struct attribute **fmt_attr;
+ const u64 capability[2];
+};
+
+struct dmc_info {
+ const struct dmc_hw_info *hw_info;
+
+ void __iomem *ddr_reg[4];
+ unsigned long timer_value; /* Timer value in TIMER register */
+ void __iomem *pll_reg;
+ int irq_num; /* irq vector number */
+};
+
+int meson_ddr_pmu_create(struct platform_device *pdev);
+int meson_ddr_pmu_remove(struct platform_device *pdev);
+
+#endif /* __MESON_DDR_PMU_H__ */