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authorChanWoo Lee <cw9316.lee@samsung.com>2024-01-02 10:42:22 +0900
committerMartin K. Petersen <martin.petersen@oracle.com>2024-01-23 21:33:28 -0500
commitab3e6c4e0ea149f16d5b719ecf7572862060d215 (patch)
tree173f70726009b138335884ffd85ff5f3f6d2b84b /include/ufs
parent796cae1a79b192510041563c95d3fc0fab31ec6e (diff)
scsi: ufs: mcq: Add definition for REG_UFS_MEM_CFG register
Instead of hardcoding the register field, add the proper definition. While at it, let's also use ufshcd_rmwl() to simplify updating this register. Reviewed-by: Peter Wang <peter.wang@mediatek.com> Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com> Link: https://lore.kernel.org/r/20240102014222.23351-1-cw9316.lee@samsung.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'include/ufs')
-rw-r--r--include/ufs/ufshcd.h1
-rw-r--r--include/ufs/ufshci.h3
2 files changed, 4 insertions, 0 deletions
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index c491671e79b7..cb2afcebbdf5 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -1267,6 +1267,7 @@ unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
struct ufs_hw_queue *hwq);
void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
+void ufshcd_mcq_enable(struct ufs_hba *hba);
void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h
index d5accacae6bc..a196e1c4c3bb 100644
--- a/include/ufs/ufshci.h
+++ b/include/ufs/ufshci.h
@@ -282,6 +282,9 @@ enum {
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
+/* REG_UFS_MEM_CFG - Global Config Registers 300h */
+#define MCQ_MODE_SELECT BIT(0)
+
/* CQISy - CQ y Interrupt Status Register */
#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1