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authorThomas Gleixner <tglx@linutronix.de>2016-11-29 14:06:00 +0100
committerThomas Gleixner <tglx@linutronix.de>2016-11-29 14:06:00 +0100
commit2cae3a1ed36ded9b4c8859feeea73827f1c2130d (patch)
tree0c8ac90f545a9c44c5199aa605e5b65d78bf07dd /include
parent4e201566402c878a225d4425df8a4a664c6f251e (diff)
parent8328255ff81ed422847b443f81b689366e98ce95 (diff)
Merge tag 'irqchip-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates for 4.10 from Marc Zyngier: - xylinx interrupt controller made architecture agnostic (microblaze, ppc, mips) - GICv3 ITS now supported on 32bit ARM (mostly useful for virtual machines) - Some arm64 GICv3 cleanups
Diffstat (limited to 'include')
-rw-r--r--include/linux/irqchip/arm-gic-v3.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index b7e34313cdfe..5118d3a0c9ca 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -239,7 +239,7 @@
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HWCOLLCNT_SHIFT 24
-#define GITS_CBASER_VALID (1UL << 63)
+#define GITS_CBASER_VALID (1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
@@ -265,7 +265,7 @@
#define GITS_BASER_NR_REGS 8
-#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_VALID (1ULL << 63)
#define GITS_BASER_INDIRECT (1ULL << 62)
#define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)