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authorRussell King <rmk+kernel@armlinux.org.uk>2020-05-26 11:36:10 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2020-06-03 14:53:34 +0100
commit5a69c339bbd2b5e8aa5e08204b55bb0f17bf8a7a (patch)
tree38e586e126f27197ba3dd8cbd9ffa0a12528a045 /include
parente03c23a52a59e7f2d71316379bc224344b6c2ffc (diff)
net: mdiobus: add clause 45 mdiobus accessors
There is a recurring pattern throughout some of the PHY code converting a devad and regnum to our packed clause 45 representation. Rather than having this scattered around the code, let's put a common translation function in mdio.h, and provide some register accessors. Convert the phylib core, phylink, bcm87xx and cortina to use these. Acked-by: Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mdio.h31
-rw-r--r--include/linux/phy.h6
2 files changed, 31 insertions, 6 deletions
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 917e4bb2ed71..36d2e0673d03 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -9,6 +9,13 @@
#include <uapi/linux/mdio.h>
#include <linux/mod_devicetable.h>
+/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
+ * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
+ */
+#define MII_ADDR_C45 (1<<30)
+#define MII_DEVADDR_C45_SHIFT 16
+#define MII_REGADDR_C45_MASK GENMASK(15, 0)
+
struct gpio_desc;
struct mii_bus;
@@ -326,6 +333,30 @@ int mdiobus_write_nested(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask,
u16 set);
+static inline u32 mdiobus_c45_addr(int devad, u16 regnum)
+{
+ return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;
+}
+
+static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
+ u16 regnum)
+{
+ return __mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum));
+}
+
+static inline int __mdiobus_c45_write(struct mii_bus *bus, int prtad, int devad,
+ u16 regnum, u16 val)
+{
+ return __mdiobus_write(bus, prtad, mdiobus_c45_addr(devad, regnum),
+ val);
+}
+
+static inline int mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,
+ u16 regnum)
+{
+ return mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum));
+}
+
int mdiobus_register_device(struct mdio_device *mdiodev);
int mdiobus_unregister_device(struct mdio_device *mdiodev);
bool mdiobus_is_registered_device(struct mii_bus *bus, int addr);
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 2432ca463ddc..08a41340d88a 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -206,12 +206,6 @@ static inline const char *phy_modes(phy_interface_t interface)
#define MII_BUS_ID_SIZE 61
-/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
- IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */
-#define MII_ADDR_C45 (1<<30)
-#define MII_DEVADDR_C45_SHIFT 16
-#define MII_REGADDR_C45_MASK GENMASK(15, 0)
-
struct device;
struct phylink;
struct sfp_bus;