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| author | Thomas Gleixner <tglx@linutronix.de> | 2023-07-24 10:27:43 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2023-07-24 10:27:43 +0200 |
| commit | de990908521073d98a46ad0e29885df447e95242 (patch) | |
| tree | 7fdb3c7a9c963290138c660749591d8b63085dde /kernel/irq/resend.c | |
| parent | 67a4e1a3bf7c68ed3fbefc4213648165d912cabb (diff) | |
| parent | 6fe5c68ee6a1aae0ef291a56001e7888de547fa2 (diff) | |
Merge tag 'irqchip-fixes-6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier:
- Work around an erratum on GIC700, where a race between a CPU
handling a wake-up interrupt, a change of affinity, and another
CPU going to sleep can result in a lack of wake-up event on the
next interrupt.
- Fix the locking required on a VPE for GICv4
- Enable Rockchip 3588001 erratum workaround for RK3588S
- Fix the irq-bcm6345-l1 assumtions of the boot CPU always be
the first CPU in the system
Link: https://lore.kernel.org/lkml/20230717113857.304919-1-maz@kernel.org
Diffstat (limited to 'kernel/irq/resend.c')
0 files changed, 0 insertions, 0 deletions