diff options
| author | Ye Li <ye.li@nxp.com> | 2023-06-25 20:33:39 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2023-08-14 12:29:52 +0300 |
| commit | 3f0cdb945471f1abd1cf4d172190e9c489c5052a (patch) | |
| tree | 80991174993ac1fb7e8c6fa3dc971fdf60bba620 /mm/dmapool.c | |
| parent | d3a0946d7ac9ad844a196f0f2af696fde6b0728d (diff) | |
clk: imx: pllv4: Fix SPLL2 MULT range
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
using a range from 27 to 54, not some fixed values. If using
current PLL implementation, some clock rate can't be supported.
Fix the issue by adding new type for the SPLL2 and use MULT range
to replace MULT table
Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'mm/dmapool.c')
0 files changed, 0 insertions, 0 deletions