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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-02-06 17:33:46 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-02-13 10:16:04 -0200 |
| commit | 186a277e317a14dcba5a2d709f2fbd8c078dfa6f (patch) | |
| tree | 99fadebdcef48833e917488745a41ef7edaf3095 /security/Makefile | |
| parent | 62d4a5e149552ef1f1757197652ae7be4fc9f3a3 (diff) | |
drm/i915/icl: add the main CDCLK functions
This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.
v2:
- Implement the voltage levels.
- Rebase.
v3:
- Adjust to the new "bypass" clock (Imre).
- Call intel_dump_cdclk_state() too.
- Rename a variable to avoid confusion.
- Simplify the DVFS part.
v4:
- Remove wrong bit definition (James).
- Also drive-by fix the coding style for the register definition we
touched.
v5:
- Comment style (checkpatch).
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180206193346.18272-1-paulo.r.zanoni@intel.com
Diffstat (limited to 'security/Makefile')
0 files changed, 0 insertions, 0 deletions