diff options
| author | Oder Chiou <oder_chiou@realtek.com> | 2014-11-11 15:31:19 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-11-12 11:48:40 +0000 |
| commit | 91159ecaf4401f7b4b0d48f59c877a0779209af5 (patch) | |
| tree | e894f516c4cc179d8c4a3e14a8ec072698b3cfc6 /sound/soc/codecs/rt5677.h | |
| parent | 19ba484d7b15c8650b30377aad6e65b34d3cf3d5 (diff) | |
ASoC: rt5677: Add TDM channel mux in DAC side of IF1 and IF2
It is the slot selection in DAC side of IF1 and IF2.
Signed-off-by: Oder Chiou <oder_chiou@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/rt5677.h')
| -rw-r--r-- | sound/soc/codecs/rt5677.h | 48 |
1 files changed, 44 insertions, 4 deletions
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index 9d473b2798d5..2979d5a05789 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -799,7 +799,7 @@ #define RT5677_PDM2_I2C_EXE (0x1 << 1) #define RT5677_PDM2_I2C_BUSY (0x1 << 0) -/* MX3B TDM1 control 1 (0x3b) */ +/* TDM1 control 1 (0x3b) */ #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12) #define RT5677_IF1_ADC_MODE_SFT 12 #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12) @@ -813,7 +813,7 @@ #define RT5677_IF1_ADC4_SWAP_MASK (0x3 << 0) #define RT5677_IF1_ADC4_SWAP_SFT 0 -/* MX3C TDM1 control 2 (0x3c) */ +/* TDM1 control 2 (0x3c) */ #define RT5677_IF1_ADC4_MASK (0x3 << 10) #define RT5677_IF1_ADC4_SFT 10 #define RT5677_IF1_ADC3_MASK (0x3 << 8) @@ -825,7 +825,27 @@ #define RT5677_IF1_ADC_CTRL_MASK (0x7 << 0) #define RT5677_IF1_ADC_CTRL_SFT 0 -/* MX40 TDM2 control 1 (0x40) */ +/* TDM1 control 4 (0x3e) */ +#define RT5677_IF1_DAC0_MASK (0x7 << 12) +#define RT5677_IF1_DAC0_SFT 12 +#define RT5677_IF1_DAC1_MASK (0x7 << 8) +#define RT5677_IF1_DAC1_SFT 8 +#define RT5677_IF1_DAC2_MASK (0x7 << 4) +#define RT5677_IF1_DAC2_SFT 4 +#define RT5677_IF1_DAC3_MASK (0x7 << 0) +#define RT5677_IF1_DAC3_SFT 0 + +/* TDM1 control 5 (0x3f) */ +#define RT5677_IF1_DAC4_MASK (0x7 << 12) +#define RT5677_IF1_DAC4_SFT 12 +#define RT5677_IF1_DAC5_MASK (0x7 << 8) +#define RT5677_IF1_DAC5_SFT 8 +#define RT5677_IF1_DAC6_MASK (0x7 << 4) +#define RT5677_IF1_DAC6_SFT 4 +#define RT5677_IF1_DAC7_MASK (0x7 << 0) +#define RT5677_IF1_DAC7_SFT 0 + +/* TDM2 control 1 (0x40) */ #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12) #define RT5677_IF2_ADC_MODE_SFT 12 #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12) @@ -839,7 +859,7 @@ #define RT5677_IF2_ADC4_SWAP_MASK (0x3 << 0) #define RT5677_IF2_ADC4_SWAP_SFT 0 -/* MX41 TDM2 control 2 (0x41) */ +/* TDM2 control 2 (0x41) */ #define RT5677_IF2_ADC4_MASK (0x3 << 10) #define RT5677_IF2_ADC4_SFT 10 #define RT5677_IF2_ADC3_MASK (0x3 << 8) @@ -851,6 +871,26 @@ #define RT5677_IF2_ADC_CTRL_MASK (0x7 << 0) #define RT5677_IF2_ADC_CTRL_SFT 0 +/* TDM2 control 4 (0x43) */ +#define RT5677_IF2_DAC0_MASK (0x7 << 12) +#define RT5677_IF2_DAC0_SFT 12 +#define RT5677_IF2_DAC1_MASK (0x7 << 8) +#define RT5677_IF2_DAC1_SFT 8 +#define RT5677_IF2_DAC2_MASK (0x7 << 4) +#define RT5677_IF2_DAC2_SFT 4 +#define RT5677_IF2_DAC3_MASK (0x7 << 0) +#define RT5677_IF2_DAC3_SFT 0 + +/* TDM2 control 5 (0x44) */ +#define RT5677_IF2_DAC4_MASK (0x7 << 12) +#define RT5677_IF2_DAC4_SFT 12 +#define RT5677_IF2_DAC5_MASK (0x7 << 8) +#define RT5677_IF2_DAC5_SFT 8 +#define RT5677_IF2_DAC6_MASK (0x7 << 4) +#define RT5677_IF2_DAC6_SFT 4 +#define RT5677_IF2_DAC7_MASK (0x7 << 0) +#define RT5677_IF2_DAC7_SFT 0 + /* Digital Microphone Control 1 (0x50) */ #define RT5677_DMIC_1_EN_MASK (0x1 << 15) #define RT5677_DMIC_1_EN_SFT 15 |