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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2015-06-04 16:04:16 +0300
committerMark Brown <broonie@kernel.org>2015-06-04 17:50:02 +0100
commit89683fdefdd74828145b9d18333761cc975143f8 (patch)
treebaccb272b4134abd5a49d2341739f743f7d14408 /sound/soc/codecs/tas2552.c
parent1cf0f44811b754b64283b11ef0e60cb0de07b29c (diff)
ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1. PDM_DATA_ES bit is at bit2. The code were trying to select BCLK as PDM reference clock but instead it was selecting PLL and set the DATA_ES bit to 1. Selecting the PLL output as reference clock as default does make sense, but the driver should not change the PDM data edge. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/tas2552.c')
-rw-r--r--sound/soc/codecs/tas2552.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c
index 9954bd4c14f3..07a0ec03905d 100644
--- a/sound/soc/codecs/tas2552.c
+++ b/sound/soc/codecs/tas2552.c
@@ -376,7 +376,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec)
TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);
snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I);
snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8);
- snd_soc_write(codec, TAS2552_PDM_CFG, TAS2552_PDM_BCLK_SEL);
+ snd_soc_write(codec, TAS2552_PDM_CFG, TAS2552_PDM_CLK_SEL_PLL);
snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 |
TAS2552_APT_THRESH_2_1_7);