diff options
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2015-06-08 15:19:48 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-06-08 18:53:18 +0100 |
| commit | 1014f7eff9a1d4f3f796c83e933adf2462c79005 (patch) | |
| tree | 59ca30454a1d0dfe14c675e40ad15e8dbd5d0f91 /sound/soc/codecs/tas2552.h | |
| parent | a571cb17acb6156e6ea8d5fe2ff824e713416bae (diff) | |
ASoC: tas2552: Correct the PLL configuration
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should
be (sampling rate * 512) in all cases.
Correct the J.D calculation (the D part was incorrectly calculated).
Restore PLL enable status after we are done with the configuration.
Implement hardware constraint handling towards the pll_clkin:
if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked.
If the PLL setup does not met with this constraint, fall back to BCLK as
reference clock, if BCLK fails, use the internal 1.8MHz clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/tas2552.h')
| -rw-r--r-- | sound/soc/codecs/tas2552.h | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/sound/soc/codecs/tas2552.h b/sound/soc/codecs/tas2552.h index bbb820495516..6806516a62cd 100644 --- a/sound/soc/codecs/tas2552.h +++ b/sound/soc/codecs/tas2552.h @@ -128,12 +128,9 @@ #define TAS2552_APT_THRESH_2_1_7 (0x11 << 2) /* PLL Control Register */ -#define TAS2552_245MHZ_CLK 24576000 -#define TAS2552_225MHZ_CLK 22579200 -#define TAS2552_PLL_J_MASK 0x7f -#define TAS2552_PLL_D_UPPER_MASK 0x3f -#define TAS2552_PLL_D_LOWER_MASK 0xff -#define TAS2552_PLL_BYPASS_MASK 0x80 -#define TAS2552_PLL_BYPASS 0x80 +#define TAS2552_PLL_J_MASK 0x7f +#define TAS2552_PLL_D_UPPER(x) (((x) >> 8) & 0x3f) +#define TAS2552_PLL_D_LOWER(x) ((x) & 0xff) +#define TAS2552_PLL_BYPASS (1 << 7) #endif |