diff options
| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2017-09-08 12:43:52 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-09-19 14:36:18 +0100 |
| commit | 7735bce05a9c0bb0eb0f08c9002d65843a7c5798 (patch) | |
| tree | b61861e2ac67aa1ec702f6e02a868fff11ba3814 /sound/soc/intel/boards/bytcr_rt5640.c | |
| parent | 86cb5dee237be6cf6c432299b829a5e85ed35029 (diff) | |
ASoC: Intel: boards: use devm_clk_get() unconditionally
The clock framework was only used in Baytrail, on Cherrytrail
the firmware takes care of the MCLK/plt_clk_3.
With the fix in 'commit d31fd43c0f9a
("clk: x86: Do not gate clocks enabled by the firmware")'
the firmware-managed clocks are not impacted by enable/disable
requests make at the driver level, and the rates are identical.
Remove all checks for Baytrail and use devm_clk_get()
unconditionally. Tested on Asus T100HA (CHT) and Asus T100TAF (BYT)
Note that the RT5640 and RT5645 machine drivers need to keep some
checks for Valleyview to check for Baytrail-CR.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-By: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/boards/bytcr_rt5640.c')
| -rw-r--r-- | sound/soc/intel/boards/bytcr_rt5640.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c index 4a76b099a508..15b1e292b0c3 100644 --- a/sound/soc/intel/boards/bytcr_rt5640.c +++ b/sound/soc/intel/boards/bytcr_rt5640.c @@ -891,7 +891,7 @@ static int snd_byt_rt5640_mc_probe(struct platform_device *pdev) byt_rt5640_cpu_dai_name; } - if ((byt_rt5640_quirk & BYT_RT5640_MCLK_EN) && (is_valleyview())) { + if (byt_rt5640_quirk & BYT_RT5640_MCLK_EN) { priv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3"); if (IS_ERR(priv->mclk)) { ret_val = PTR_ERR(priv->mclk); |