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authorJörg Krause <joerg.krause@embedded.rocks>2017-01-13 21:44:28 +0100
committerMark Brown <broonie@kernel.org>2017-01-17 18:19:36 +0000
commitb25658ed7d24cd8b1f9a72148e80e216b6a0c17a (patch)
tree83e19bcd6583ce3aa7bb945105bdda94fd85db84 /sound/soc/mxs
parenta5de5b74a50113564a1e0850e2da96c37c35e55d (diff)
ASoC: mxs-saif: fix setting SAIF1 register
If SAIF0 is used in master and SAIF1 in slave mode setting the SAIF1 register in mxs_saif_set_dai_fmt() does not have any effect on the interface as the clk gate needs to be cleared before the register can be written. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/mxs')
-rw-r--r--sound/soc/mxs/mxs-saif.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index a002ab892772..9012a2036131 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -299,6 +299,16 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
return -EBUSY;
}
+ /* If SAIF1 is configured as slave, the clk gate needs to be cleared
+ * before the register can be written.
+ */
+ if (saif->id != saif->master_id) {
+ __raw_writel(BM_SAIF_CTRL_SFTRST,
+ saif->base + SAIF_CTRL + MXS_CLR_ADDR);
+ __raw_writel(BM_SAIF_CTRL_CLKGATE,
+ saif->base + SAIF_CTRL + MXS_CLR_ADDR);
+ }
+
scr0 = __raw_readl(saif->base + SAIF_CTRL);
scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;