Merge tag 'sound-5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "Lots of code development have been see in ASoC side as usual, while
  the continued development on memalloc helper and USB-audio low-
  latency support are found in the rest.

  Note that a few changes in the unusual places like arch/sh are
  included, which are a part of ASoC DAI format cleanups.

  ALSA core:

   - Continued memalloc helper updates and cleanups, now supporting
     non-coherent and non-contiguous pages

   - Fixes for races in mixer OSS layer

  ASoC:

   - A new version of the audio graph card which supports a wider range
     of systems

   - Several conversions to YAML DT bindings

   - Continuing cleanups to the SOF and Intel code

   - Move of the Cirrus DSP framework into drivers/firmware to allow for
     future use by non-audio DSPs

   - An overhaul of the cs42l42 driver, correcting many problems

   - DAI format terminology conversions over many drivers for cleanups

   - Support for AMD Vangogh and Yelow Cap, Cirrus CS35L41, Maxim
     MAX98520 and MAX98360A, Mediatek MT8195, Nuvoton NAU8821, nVidia
     Tegra210, NXP i.MX8ULP, Qualcomm AudioReach, Realtek ALC5682I-VS,
     RT5682S, and RT9120 and Rockchip RV1126 and RK3568

  USB-audio:

   - Continued improvements on low-latency playback

   - Quirks for Pioneer devices, Line6 HX-Stomp XL, Audient iD14

  HD-audio:

   - Reduce excessive udelay() calls on Intel platforms; this should
     reduce the CPU load with PulseAudio

   - Quirks for HP and Clevo laptops

  FireWire:

   - Support for meter information on MOTU"

* tag 'sound-5.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (513 commits)
  ALSA: usb-audio: Add quirk for Audient iD14
  ALSA: hda/realtek: Add quirk for Clevo PC70HS
  ALSA: usb-audio: Line6 HX-Stomp XL USB_ID for 48k-fixed quirk
  ALSA: usb-audio: Add registration quirk for JBL Quantum 400
  ASoC: rsnd: Fix an error handling path in 'rsnd_node_count()'
  ASoC: tlv320aic3x: Make aic3x_remove() return void
  ASoC: Intel: soc-acpi: use const for all uses of snd_soc_acpi_codecs
  ASoC: Intel: soc-acpi-cht: shrink tables using compatible IDs
  ASoC: Intel: soc-acpi-byt: shrink tables using compatible IDs
  ASoC: Intel: sof_rt5682: use comp_ids to enumerate rt5682s
  ASoC: Intel: sof_rt5682: detect codec variant in probe function
  ASoC: soc-acpi: add comp_ids field for machine driver matching
  ASoC: mediatek: mt8195: add mt8195-mt6359-rt1011-rt5682 bindings document
  ASoC: mediatek: mt8195: add machine driver with mt6359, rt1011 and rt5682
  ASoC: Stop dummy from overriding hwparams
  ASoC: topology: Change topology device to card device
  ASoC: topology: Use correct device for prints
  ASoC: topology: Check for dapm widget completeness
  ASoC: topology: Add header payload_size verification
  ASoC: core: Remove invalid snd_soc_component_set_jack call
  ...

1 files changed, 78 insertions, 0 deletions

diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
new file mode 100644
index 000000000000..fea4d1954bc1
--- /dev/null
+++ b/sound/soc/qcom/qdsp6/q6prm.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __Q6PRM_H__
+#define __Q6PRM_H__
+
+/* Clock ID for Primary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT                          0x100
+/* Clock ID for Primary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT                          0x101
+/* Clock ID for Secondary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT                          0x102
+/* Clock ID for Secondary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT                          0x103
+/* Clock ID for Tertiary I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT                          0x104
+/* Clock ID for Tertiary I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT                          0x105
+/* Clock ID for Quartnery I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT                         0x106
+/* Clock ID for Quartnery I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT                         0x107
+/* Clock ID for Speaker I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT                       0x108
+/* Clock ID for Speaker I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT                       0x109
+/* Clock ID for Speaker I2S OSR */
+#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR                        0x10A
+
+/* Clock ID for QUINARY  I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT			0x10B
+/* Clock ID for QUINARY  I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT			0x10C
+/* Clock ID for SENARY  I2S IBIT */
+#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT			0x10D
+/* Clock ID for SENARY  I2S EBIT */
+#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT			0x10E
+/* Clock ID for INT0 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT                       0x10F
+/* Clock ID for INT1 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT                       0x110
+/* Clock ID for INT2 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT                       0x111
+/* Clock ID for INT3 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT                       0x112
+/* Clock ID for INT4 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT                       0x113
+/* Clock ID for INT5 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT                       0x114
+/* Clock ID for INT6 I2S IBIT  */
+#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT                       0x115
+
+/* Clock ID for QUINARY MI2S OSR CLK  */
+#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR                         0x116
+
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK			0x305
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK			0x306
+
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK				0x307
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK			0x308
+
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK				0x30c
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK			0x30d
+
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK				0x30e
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK			0x30f
+
+#define Q6PRM_LPASS_CLK_SRC_INTERNAL	1
+#define Q6PRM_LPASS_CLK_ROOT_DEFAULT	0
+#define Q6PRM_HW_CORE_ID_LPASS		1
+#define Q6PRM_HW_CORE_ID_DCODEC		2
+
+int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
+			  int clk_root, unsigned int freq);
+int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
+			     const char *client_name, uint32_t *client_handle);
+int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
+			       uint32_t client_handle);
+#endif /* __Q6PRM_H__ */