diff options
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2015-06-04 16:04:16 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-06-04 17:50:02 +0100 |
| commit | 89683fdefdd74828145b9d18333761cc975143f8 (patch) | |
| tree | baccb272b4134abd5a49d2341739f743f7d14408 /sound/soc | |
| parent | 1cf0f44811b754b64283b11ef0e60cb0de07b29c (diff) | |
ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.
The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc')
| -rw-r--r-- | sound/soc/codecs/tas2552.c | 2 | ||||
| -rw-r--r-- | sound/soc/codecs/tas2552.h | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c index 9954bd4c14f3..07a0ec03905d 100644 --- a/sound/soc/codecs/tas2552.c +++ b/sound/soc/codecs/tas2552.c @@ -376,7 +376,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec) TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ); snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I); snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8); - snd_soc_write(codec, TAS2552_PDM_CFG, TAS2552_PDM_BCLK_SEL); + snd_soc_write(codec, TAS2552_PDM_CFG, TAS2552_PDM_CLK_SEL_PLL); snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 | TAS2552_APT_THRESH_2_1_7); diff --git a/sound/soc/codecs/tas2552.h b/sound/soc/codecs/tas2552.h index 6cea8f31bf88..938d90f1cab9 100644 --- a/sound/soc/codecs/tas2552.h +++ b/sound/soc/codecs/tas2552.h @@ -99,12 +99,12 @@ #define TAS2552_PDM_DATA_V_I (0x11 << 6) /* PDM CFG Register */ -#define TAS2552_PDM_DATA_ES_RISE 0x4 - -#define TAS2552_PDM_PLL_CLK_SEL 0x00 -#define TAS2552_PDM_IV_CLK_SEL (1 << 1) -#define TAS2552_PDM_BCLK_SEL (1 << 2) -#define TAS2552_PDM_MCLK_SEL (1 << 3) +#define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0) +#define TAS2552_PDM_CLK_SEL_IVCLKIN (0x1 << 0) +#define TAS2552_PDM_CLK_SEL_BCLK (0x2 << 0) +#define TAS2552_PDM_CLK_SEL_MCLK (0x3 << 0) +#define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK +#define TAS2552_PDM_DATA_ES (1 << 2) /* Boost pass-through register */ #define TAS2552_APT_DELAY_50 0x00 |