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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-12-10 20:38:32 +0800
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-12-11 03:01:09 +0800
commit37d5993c5cc9bc83762ae1b5bd287438022e8afe (patch)
tree9d05123c5b167ab8bb3b815e5becf537d54bfd92 /sound
parent974edd30beafdb136cdfc6839a143e23c826dc89 (diff)
ASoC: Fix WM8996 24.576MHz clock operation
Record the clock after the divider as that is what all SYSCLK users see. Without this the other clock configuration in the device comes out at half rate. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: stable@kernel.org
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/wm8996.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index 645c980d6b80..a33b04d17195 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -1968,6 +1968,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
break;
case 24576000:
ratediv = WM8996_SYSCLK_DIV;
+ wm8996->sysclk /= 2;
case 12288000:
snd_soc_update_bits(codec, WM8996_AIF_RATE,
WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);