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authorArnaud Mouiche <arnaud.mouiche@invoxia.com>2016-05-03 14:13:59 +0200
committerMark Brown <broonie@kernel.org>2016-05-13 12:15:31 +0100
commit61fcf10a0ee44763e0347b297a377137f8950772 (patch)
treef99e6486347127bf1bc6f3aad69c83edc237711a /sound
parentd9f2a202877c15818d98268f47d6b4bcfcb84437 (diff)
ASoC: fsl_ssi: Fix channel slipping in Playback at startup
Previously, SCR.SSIEN and SCR.TE were enabled at once if no capture stream was also running. This may not give a chance for the DMA to write the first sample in TX FIFO before the streaming starts on the PCM bus, inserting void samples first. Those void samples are then responsible for slipping the channels. Signed-off-by: Arnaud Mouiche <arnaud.mouiche@invoxia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Caleb Crome <caleb@crome.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/fsl/fsl_ssi.c34
1 files changed, 33 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 47ebb835f3f5..8944af542b4f 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -507,8 +507,40 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
config_done:
/* Enabling of subunits is done after configuration */
- if (enable)
+ if (enable) {
+ if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) {
+ /*
+ * Be sure the Tx FIFO is filled when TE is set.
+ * Otherwise, there are some chances to start the
+ * playback with some void samples inserted first,
+ * generating a channel slip.
+ *
+ * First, SSIEN must be set, to let the FIFO be filled.
+ *
+ * Notes:
+ * - Limit this fix to the DMA case until FIQ cases can
+ * be tested.
+ * - Limit the length of the busy loop to not lock the
+ * system too long, even if 1-2 loops are sufficient
+ * in general.
+ */
+ int i;
+ int max_loop = 100;
+ regmap_update_bits(regs, CCSR_SSI_SCR,
+ CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN);
+ for (i = 0; i < max_loop; i++) {
+ u32 sfcsr;
+ regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr);
+ if (CCSR_SSI_SFCSR_TFCNT0(sfcsr))
+ break;
+ }
+ if (i == max_loop) {
+ dev_err(ssi_private->dev,
+ "Timeout waiting TX FIFO filling\n");
+ }
+ }
regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
+ }
}