Merge tag 'perf-urgent-for-mingo-5.1-20190502' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent

Pull perf/urgent fixes from Arnaldo Carvalho de Melo:

tools UAPI:

  Arnaldo Carvalho de Melo:

  - Sync x86's vmx.h with the kernel.

  - Copy missing unistd.h headers for arc, hexagon and riscv, fixing
    a reported build regression on the ARC 32-bit architecture.

perf bench numa:

  Arnaldo Carvalho de Melo:

  - Add define for RUSAGE_THREAD if not present, fixing the build on the
    ARC architecture when only zlib and libnuma are present.

perf BPF:

  Arnaldo Carvalho de Melo:

  - The disassembler-four-args feature test needs -ldl on distros such as
    Mageia 7.

  Bo YU:

  - Fix unlocking on success in perf_env__find_btf(), detected with
    the coverity tool.

libtraceevent:

  Leo Yan:

  - Change misleading hard coded 'trace-cmd' string in error messages.

ARM hardware tracing:

  Leo Yan:

  - Always allocate memory for cs_etm_queue::prev_packet, fixing a segfault
    when processing CoreSight perf data.

perf annotate:

  Thadeu Lima de Souza Cascardo:

  - Fix build on 32 bit for BPF.

perf report:

  Thomas Richter:

  - Report OOM in status line in the GTK UI.

core libs:

  - Remove needless asm/unistd.h that, used with sys/syscall.h ended
    up redefining the syscalls defines in environments such as the
    ARC arch when using uClibc.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 42 insertions, 0 deletions

diff --git a/tools/arch/riscv/include/uapi/asm/unistd.h b/tools/arch/riscv/include/uapi/asm/unistd.h
new file mode 100644
index 000000000000..0e2eeeb1fd27
--- /dev/null
+++ b/tools/arch/riscv/include/uapi/asm/unistd.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef __LP64__
+#define __ARCH_WANT_NEW_STAT
+#define __ARCH_WANT_SET_GET_RLIMIT
+#endif /* __LP64__ */
+
+#include <asm-generic/unistd.h>
+
+/*
+ * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
+ * having a direct 'fence.i' instruction available to userspace (which we
+ * can't trap!), that's not actually viable when running on Linux because the
+ * kernel might schedule a process on another hart.  There is no way for
+ * userspace to handle this without invoking the kernel (as it doesn't know the
+ * thread->hart mappings), so we've defined a RISC-V specific system call to
+ * flush the instruction cache.
+ *
+ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
+ * address range, with the flush applying to either all threads or just the
+ * caller.  We don't currently do anything with the address range, that's just
+ * in there for forwards compatibility.
+ */
+#ifndef __NR_riscv_flush_icache
+#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
+#endif
+__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)