diff options
author | Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> | 2016-09-15 18:09:30 -0400 |
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committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2016-10-17 13:39:47 -0300 |
commit | 2a81fa3bb5edb4a9dc9cb04cd591c99d41eb4f4c (patch) | |
tree | 985a5453e92f43104df951fceeaf74bf2ef7f998 /tools/perf/pmu-events/arch/powerpc/power8/translation.json | |
parent | 1fbd54b2e2356659f9f87920dc514792db6ff602 (diff) |
perf vendor events: Add power8 PMU events
Add mapfile.csv and power8.json files for the Power8 processor.
Changelog[v3]
- [Namhyung Kim] Remove text from PublicDescription fields if it is
identical to or prefix of BriefDescription.
Changelog[v2]
- [Andi Kleen] Replace the vendor-family-model,version fields with
cpuid,version fields (to simplify mapfile)
- Reuse the JSON files when possible (i.e multiple cpuids can refer
to the same JSON file) - so drop the 004d0100.json and use
power8.json in multiple entries in mapfile.
- Add few more Power8 PVRs to mapfile
Changelog[v21]
- Group events into per topic per cpu model.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
CC: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Link: http://lkml.kernel.org/n/tip-wr6rf3d3vvggy8180ftt2ro1@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power8/translation.json')
-rw-r--r-- | tools/perf/pmu-events/arch/powerpc/power8/translation.json | 176 |
1 files changed, 176 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power8/translation.json b/tools/perf/pmu-events/arch/powerpc/power8/translation.json new file mode 100644 index 000000000000..e47a55459bc8 --- /dev/null +++ b/tools/perf/pmu-events/arch/powerpc/power8/translation.json @@ -0,0 +1,176 @@ +[ + {, + "EventCode": "0x4c054", + "EventName": "PM_DERAT_MISS_16G", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c054", + "EventName": "PM_DERAT_MISS_16M", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", + "PublicDescription": "" + }, + {, + "EventCode": "0x1c056", + "EventName": "PM_DERAT_MISS_4K", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c054", + "EventName": "PM_DERAT_MISS_64K", + "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e048", + "EventName": "PM_DPTEG_FROM_DL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e048", + "EventName": "PM_DPTEG_FROM_DL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e042", + "EventName": "PM_DPTEG_FROM_L2", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e04e", + "EventName": "PM_DPTEG_FROM_L2MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e040", + "EventName": "PM_DPTEG_FROM_L2_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e040", + "EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e042", + "EventName": "PM_DPTEG_FROM_L3", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x3e042", + "EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e042", + "EventName": "PM_DPTEG_FROM_L3_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e044", + "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e04c", + "EventName": "PM_DPTEG_FROM_LL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e048", + "EventName": "PM_DPTEG_FROM_LMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e04c", + "EventName": "PM_DPTEG_FROM_MEMORY", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x4e04a", + "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e048", + "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE", + "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e046", + "EventName": "PM_DPTEG_FROM_RL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x1e04a", + "EventName": "PM_DPTEG_FROM_RL2L3_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x2e04a", + "EventName": "PM_DPTEG_FROM_RL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request", + "PublicDescription": "" + }, + {, + "EventCode": "0x300fc", + "EventName": "PM_DTLB_MISS", + "BriefDescription": "Data PTEG reload", + "PublicDescription": "Data PTEG Reloaded (DTLB Miss)" + }, + {, + "EventCode": "0x1c058", + "EventName": "PM_DTLB_MISS_16G", + "BriefDescription": "Data TLB Miss page size 16G", + "PublicDescription": "" + }, + {, + "EventCode": "0x4c056", + "EventName": "PM_DTLB_MISS_16M", + "BriefDescription": "Data TLB Miss page size 16M", + "PublicDescription": "" + }, + {, + "EventCode": "0x2c056", + "EventName": "PM_DTLB_MISS_4K", + "BriefDescription": "Data TLB Miss page size 4k", + "PublicDescription": "" + }, + {, + "EventCode": "0x3c056", + "EventName": "PM_DTLB_MISS_64K", + "BriefDescription": "Data TLB Miss page size 64K", + "PublicDescription": "" + }, + {, + "EventCode": "0x200f6", + "EventName": "PM_LSU_DERAT_MISS", + "BriefDescription": "DERAT Reloaded due to a DERAT miss", + "PublicDescription": "DERAT Reloaded (Miss)" + }, + {, + "EventCode": "0x20066", + "EventName": "PM_TLB_MISS", + "BriefDescription": "TLB Miss (I + D)", + "PublicDescription": "" + }, +] |