diff options
| author | Andi Kleen <ak@linux.intel.com> | 2016-10-05 09:53:09 -0700 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2016-10-17 13:39:47 -0300 |
| commit | d910f0ba6d72a0917ae30b6aed5131988e3096e4 (patch) | |
| tree | 72f707d572570cfaa89b19286a5fddb284904be0 /tools/perf/pmu-events/arch/x86/ivytown/other.json | |
| parent | 4b90798ebb0bab8fe1ed9065e80879503f5601d2 (diff) | |
perf vendor events: Add IvyTown V19 event file
Add a Intel event file for perf.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-p5mtp091orxty69pot9vd6ga@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/ivytown/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/ivytown/other.json | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf/pmu-events/arch/x86/ivytown/other.json new file mode 100644 index 000000000000..9c2dd0511a32 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "CPL_CYCLES.RING0", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "CPL_CYCLES.RING123", + "SampleAfterValue": "2000003", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", + "EventCode": "0x5C", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EdgeDetect": "1", + "EventName": "CPL_CYCLES.RING0_TRANS", + "SampleAfterValue": "100007", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "CounterMask": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7" + }, + { + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "EventCode": "0x63", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "SampleAfterValue": "2000003", + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", + "CounterHTOff": "0,1,2,3,4,5,6,7" + } +]
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