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| author | Zhang Rui <rui.zhang@intel.com> | 2023-10-19 11:04:33 +0800 |
|---|---|---|
| committer | Zhang Rui <rui.zhang@intel.com> | 2023-10-24 13:38:09 +0800 |
| commit | 0e3f10e6aa97b0134b526ec9cdc3ccdac2239b43 (patch) | |
| tree | 3214aeb9752b60f6eab2014bbf49826312fd824e /tools/power | |
| parent | 37f68a2940558b4f6f8e51b7b1d00f084b4bdde2 (diff) | |
tools/power/turbostat: Add MSR_CORE_C1_RES support for spr_features
Add MSR_CORE_C1_RES support for spr_features because both Sapphirerapids
and Emeraldrapids support this MSR.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Diffstat (limited to 'tools/power')
| -rw-r--r-- | tools/power/x86/turbostat/turbostat.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index fea63d9d8e02..bbeeec02bf5b 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -667,6 +667,7 @@ static const struct platform_features spr_features = { .bclk_freq = BCLK_100MHZ, .supported_cstates = CC1 | CC6 | PC2 | PC6, .cst_limit = CST_LIMIT_SKX, + .has_msr_core_c1_res = 1, .has_irtl_msrs = 1, .has_cst_prewake_bit = 1, .trl_msrs = TRL_BASE | TRL_CORECOUNT, |