diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2022-01-23 16:29:21 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:28 -0800 |
| commit | 0ff0af18216436d0151af4e410400c7a19ca9437 (patch) | |
| tree | b4982719f3e547332a73664764d0318ea4011892 /tools/testing/cxl | |
| parent | c57cae78bfa6a8535d4baade451107b0577c2750 (diff) | |
cxl/core/port: Rename bus.c to port.c
Given it is dominated by port infrastructure, and will only acquire
more, rename bus.c to port.c.
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/164298416136.3018233.15442880970000855425.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl')
| -rw-r--r-- | tools/testing/cxl/Kbuild | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 1acdf2fc31c5..3299fb0977b2 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -25,7 +25,7 @@ cxl_pmem-y += config_check.o obj-m += cxl_core.o -cxl_core-y := $(CXL_CORE_SRC)/bus.o +cxl_core-y := $(CXL_CORE_SRC)/port.o cxl_core-y += $(CXL_CORE_SRC)/pmem.o cxl_core-y += $(CXL_CORE_SRC)/regs.o cxl_core-y += $(CXL_CORE_SRC)/memdev.o |