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authorMarc Zyngier <marc.zyngier@arm.com>2017-06-09 12:49:55 +0100
committerMarc Zyngier <marc.zyngier@arm.com>2017-06-15 09:45:06 +0100
commite7f1d1eef482150a64a6e6ad8faf40f8f97eed67 (patch)
tree775d0180010de525234429766897b116b09ef769 /virt
parent2873b5082c5fbe2037f12e8d2abc8ad8f8d82a1b (diff)
KVM: arm64: Log an error if trapping a read-from-write-only GICv3 access
A read-from-write-only GICv3 access should UNDEF at EL1. But since we're in complete paranoia-land with broken CPUs, let's assume the worse and gracefully handle the case. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Christoffer Dall <cdall@linaro.org>
Diffstat (limited to 'virt')
-rw-r--r--virt/kvm/arm/hyp/vgic-v3-sr.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index 15b557697086..b26ce58b012a 100644
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -980,6 +980,8 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
break;
case SYS_ICC_EOIR0_EL1:
case SYS_ICC_EOIR1_EL1:
+ if (unlikely(is_read))
+ return 0;
fn = __vgic_v3_write_eoir;
break;
case SYS_ICC_GRPEN1_EL1:
@@ -1039,6 +1041,8 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
fn = __vgic_v3_write_bpr0;
break;
case SYS_ICC_DIR_EL1:
+ if (unlikely(is_read))
+ return 0;
fn = __vgic_v3_write_dir;
break;
case SYS_ICC_RPR_EL1: